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update gencode

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This commit is contained in:
Matthew GONG
2021-11-28 10:46:34 +08:00
parent 6f69da38f5
commit faf964370e
10 changed files with 614 additions and 568 deletions
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SIL/work/SIL_ert_shrlib_rtw/SIL.c
+601 -555
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SIL/work/SIL_ert_shrlib_rtw/SIL.h
+1 -1
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@@ -5,7 +5,7 @@
* *
* Model version : 1.659 * Model version : 1.659
* Simulink Coder version : 9.0 (R2018b) 24-May-2018 * Simulink Coder version : 9.0 (R2018b) 24-May-2018
* C/C++ source code generated on : Sat Nov 13 14:52:16 2021 * C/C++ source code generated on : Sun Nov 28 10:37:10 2021
* *
* Target selection: ert_shrlib.tlc * Target selection: ert_shrlib.tlc
* Embedded hardware selection: Intel->x86-64 (Windows64) * Embedded hardware selection: Intel->x86-64 (Windows64)
SIL/work/SIL_ert_shrlib_rtw/SIL_capi.c
+5 -5
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@@ -5,7 +5,7 @@
* *
* Model version : 1.659 * Model version : 1.659
* Simulink Coder version : 9.0 (R2018b) 24-May-2018 * Simulink Coder version : 9.0 (R2018b) 24-May-2018
* C/C++ source code generated on : Sat Nov 13 14:52:16 2021 * C/C++ source code generated on : Sun Nov 28 10:37:10 2021
* *
* Target selection: ert_shrlib.tlc * Target selection: ert_shrlib.tlc
* Embedded hardware selection: Intel->x86-64 (Windows64) * Embedded hardware selection: Intel->x86-64 (Windows64)
@@ -701,10 +701,10 @@ static rtwCAPI_ModelMappingStaticInfo mmiStatic = {
rtElementMap, rtSampleTimeMap, rtDimensionArray }, rtElementMap, rtSampleTimeMap, rtDimensionArray },
"float", "float",
{ 1333753461U, { 1985259812U,
743005813U, 1161018554U,
2716168661U, 894121781U,
1611918854U }, 1175298012U },
(NULL), 0, (NULL), 0,
0 0
}; };
SIL/work/SIL_ert_shrlib_rtw/SIL_capi.h
+1 -1
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@@ -5,7 +5,7 @@
* *
* Model version : 1.659 * Model version : 1.659
* Simulink Coder version : 9.0 (R2018b) 24-May-2018 * Simulink Coder version : 9.0 (R2018b) 24-May-2018
* C/C++ source code generated on : Sat Nov 13 14:52:16 2021 * C/C++ source code generated on : Sun Nov 28 10:37:10 2021
* *
* Target selection: ert_shrlib.tlc * Target selection: ert_shrlib.tlc
* Embedded hardware selection: Intel->x86-64 (Windows64) * Embedded hardware selection: Intel->x86-64 (Windows64)
SIL/work/SIL_ert_shrlib_rtw/SIL_data.c
+3 -3
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@@ -5,7 +5,7 @@
* *
* Model version : 1.659 * Model version : 1.659
* Simulink Coder version : 9.0 (R2018b) 24-May-2018 * Simulink Coder version : 9.0 (R2018b) 24-May-2018
* C/C++ source code generated on : Sat Nov 13 14:52:16 2021 * C/C++ source code generated on : Sun Nov 28 10:37:10 2021
* *
* Target selection: ert_shrlib.tlc * Target selection: ert_shrlib.tlc
* Embedded hardware selection: Intel->x86-64 (Windows64) * Embedded hardware selection: Intel->x86-64 (Windows64)
@@ -958,7 +958,7 @@ const ConstP_SIL_T SIL_ConstP = {
{ 0.0F, 150.0F, 1.0F, 0.0F, 0.0F }, { 0.0F, 150.0F, 1.0F, 0.0F, 0.0F },
{ 408647182, 1093592834 } { 408647182, 1093592834 }
}, { 3U, }, { 0U,
16U, 16U,
1U, 1U,
@@ -1090,7 +1090,7 @@ const ConstP_SIL_T SIL_ConstP = {
{ 1500.0F, 0.0F, 0.0F, 0.0F, 1750.0F }, { 1500.0F, 0.0F, 0.0F, 0.0F, 1750.0F },
{ 408647182, 1095288419 } { 408647182, 1095238419 }
}, { 0U, }, { 0U,
16U, 16U,
1U, 1U,
SIL/work/SIL_ert_shrlib_rtw/SIL_private.h
+1 -1
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@@ -5,7 +5,7 @@
* *
* Model version : 1.659 * Model version : 1.659
* Simulink Coder version : 9.0 (R2018b) 24-May-2018 * Simulink Coder version : 9.0 (R2018b) 24-May-2018
* C/C++ source code generated on : Sat Nov 13 14:52:16 2021 * C/C++ source code generated on : Sun Nov 28 10:37:10 2021
* *
* Target selection: ert_shrlib.tlc * Target selection: ert_shrlib.tlc
* Embedded hardware selection: Intel->x86-64 (Windows64) * Embedded hardware selection: Intel->x86-64 (Windows64)
SIL/work/SIL_ert_shrlib_rtw/SIL_types.h
+1 -1
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@@ -5,7 +5,7 @@
* *
* Model version : 1.659 * Model version : 1.659
* Simulink Coder version : 9.0 (R2018b) 24-May-2018 * Simulink Coder version : 9.0 (R2018b) 24-May-2018
* C/C++ source code generated on : Sat Nov 13 14:52:16 2021 * C/C++ source code generated on : Sun Nov 28 10:37:10 2021
* *
* Target selection: ert_shrlib.tlc * Target selection: ert_shrlib.tlc
* Embedded hardware selection: Intel->x86-64 (Windows64) * Embedded hardware selection: Intel->x86-64 (Windows64)
SIL/work/SIL_ert_shrlib_rtw/buildInfo.mat
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SIL/work/SIL_ert_shrlib_rtw/rtmodel.h
+1 -1
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@@ -5,7 +5,7 @@
* *
* Model version : 1.659 * Model version : 1.659
* Simulink Coder version : 9.0 (R2018b) 24-May-2018 * Simulink Coder version : 9.0 (R2018b) 24-May-2018
* C/C++ source code generated on : Sat Nov 13 14:52:16 2021 * C/C++ source code generated on : Sun Nov 28 10:37:10 2021
* *
* Target selection: ert_shrlib.tlc * Target selection: ert_shrlib.tlc
* Embedded hardware selection: Intel->x86-64 (Windows64) * Embedded hardware selection: Intel->x86-64 (Windows64)
SIL/work/SIL_win64.dll
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