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update gencode

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This commit is contained in:
matt
2020-12-02 09:59:07 +08:00
parent 8463e0518d
commit b064e82d9d
11 changed files with 33 additions and 37 deletions
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SIL/work/SIL_ert_shrlib_rtw/SIL.c
+16 -23
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@@ -5,7 +5,7 @@
* *
* Model version : 1.523 * Model version : 1.523
* Simulink Coder version : 9.0 (R2018b) 24-May-2018 * Simulink Coder version : 9.0 (R2018b) 24-May-2018
* C/C++ source code generated on : Wed Dec 2 07:33:19 2020 * C/C++ source code generated on : Wed Dec 2 09:48:16 2020
* *
* Target selection: ert_shrlib.tlc * Target selection: ert_shrlib.tlc
* Embedded hardware selection: Intel->x86-64 (Windows64) * Embedded hardware selection: Intel->x86-64 (Windows64)
@@ -612,7 +612,6 @@ static void SIL_sf_msg_send_cmd(void);
static void SIL_update_vert(ENUM_AFCS_VERT in, ENUM_AT in2, ENUM_AFCS_VERT *out, static void SIL_update_vert(ENUM_AFCS_VERT in, ENUM_AT in2, ENUM_AFCS_VERT *out,
ENUM_AT *out2); ENUM_AT *out2);
static void SIL_parachute(void); static void SIL_parachute(void);
static void SIL_Idle(void);
static boolean_T SIL_sf_msg_pop_msgs(void); static boolean_T SIL_sf_msg_pop_msgs(void);
static void SIL_sf_msg_send_resp(void); static void SIL_sf_msg_send_resp(void);
static void SIL_sf_msg_send_resp_i(void); static void SIL_sf_msg_send_resp_i(void);
@@ -6197,26 +6196,6 @@ static void SIL_parachute(void)
} }
} }
/* Function for Chart: '<S547>/Chart' */
static void SIL_Idle(void)
{
if ((SIL_B.merged.recovery & 1U) != 0U) {
SIL_DW.is_c59_kb3_autopilot = SIL_IN_parachute;
SIL_DW.temporalCounter_i2 = 0U;
SIL_B.recovery_out = 1U;
SIL_DW.is_parachute = SIL_IN_one;
SIL_DW.temporalCounter_i1_fn = 0U;
SIL_B.ch_out = 3U;
SIL_B.peroid_out = 50U;
SIL_B.sw_out = 1U;
} else {
SIL_B.recovery_out = SIL_B.merged.recovery;
SIL_B.ch_out = SIL_B.merged.ccm_ch;
SIL_B.peroid_out = SIL_B.merged.ccm_period;
SIL_B.sw_out = SIL_B.merged.ccm_sw;
}
}
int32_T SIL_pop_c02u1irtbrb(Queue_mavlink_message_t *q, Msg_mavlink_message_t int32_T SIL_pop_c02u1irtbrb(Queue_mavlink_message_t *q, Msg_mavlink_message_t
*elementOut) *elementOut)
{ {
@@ -18422,7 +18401,21 @@ void SIL_step(void)
} else { } else {
switch (SIL_DW.is_c59_kb3_autopilot) { switch (SIL_DW.is_c59_kb3_autopilot) {
case SIL_IN_Idle_o: case SIL_IN_Idle_o:
SIL_Idle(); if ((SIL_B.merged.recovery & 1U) != 0U) {
SIL_DW.is_c59_kb3_autopilot = SIL_IN_parachute;
SIL_DW.temporalCounter_i2 = 0U;
SIL_B.recovery_out = 1U;
SIL_DW.is_parachute = SIL_IN_one;
SIL_DW.temporalCounter_i1_fn = 0U;
SIL_B.ch_out = 3U;
SIL_B.peroid_out = 50U;
SIL_B.sw_out = 1U;
} else {
SIL_B.recovery_out = SIL_B.merged.recovery;
SIL_B.ch_out = SIL_B.merged.ccm_ch;
SIL_B.peroid_out = SIL_B.merged.ccm_period;
SIL_B.sw_out = SIL_B.merged.ccm_sw;
}
break; break;
case SIL_IN_Idle1: case SIL_IN_Idle1:
SIL/work/SIL_ert_shrlib_rtw/SIL.h
+1 -1
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@@ -5,7 +5,7 @@
* *
* Model version : 1.523 * Model version : 1.523
* Simulink Coder version : 9.0 (R2018b) 24-May-2018 * Simulink Coder version : 9.0 (R2018b) 24-May-2018
* C/C++ source code generated on : Wed Dec 2 07:33:19 2020 * C/C++ source code generated on : Wed Dec 2 09:48:16 2020
* *
* Target selection: ert_shrlib.tlc * Target selection: ert_shrlib.tlc
* Embedded hardware selection: Intel->x86-64 (Windows64) * Embedded hardware selection: Intel->x86-64 (Windows64)
SIL/work/SIL_ert_shrlib_rtw/SIL_capi.c
+5 -5
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@@ -5,7 +5,7 @@
* *
* Model version : 1.523 * Model version : 1.523
* Simulink Coder version : 9.0 (R2018b) 24-May-2018 * Simulink Coder version : 9.0 (R2018b) 24-May-2018
* C/C++ source code generated on : Wed Dec 2 07:33:19 2020 * C/C++ source code generated on : Wed Dec 2 09:48:16 2020
* *
* Target selection: ert_shrlib.tlc * Target selection: ert_shrlib.tlc
* Embedded hardware selection: Intel->x86-64 (Windows64) * Embedded hardware selection: Intel->x86-64 (Windows64)
@@ -472,10 +472,10 @@ static rtwCAPI_ModelMappingStaticInfo mmiStatic = {
rtElementMap, rtSampleTimeMap, rtDimensionArray }, rtElementMap, rtSampleTimeMap, rtDimensionArray },
"float", "float",
{ 2018390078U, { 802743795U,
3538475814U, 3370625247U,
307450848U, 1938363916U,
1694129538U }, 2287030912U },
(NULL), 0, (NULL), 0,
0 0
}; };
SIL/work/SIL_ert_shrlib_rtw/SIL_capi.h
+1 -1
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@@ -5,7 +5,7 @@
* *
* Model version : 1.523 * Model version : 1.523
* Simulink Coder version : 9.0 (R2018b) 24-May-2018 * Simulink Coder version : 9.0 (R2018b) 24-May-2018
* C/C++ source code generated on : Wed Dec 2 07:33:19 2020 * C/C++ source code generated on : Wed Dec 2 09:48:16 2020
* *
* Target selection: ert_shrlib.tlc * Target selection: ert_shrlib.tlc
* Embedded hardware selection: Intel->x86-64 (Windows64) * Embedded hardware selection: Intel->x86-64 (Windows64)
SIL/work/SIL_ert_shrlib_rtw/SIL_data.c
+1 -1
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@@ -5,7 +5,7 @@
* *
* Model version : 1.523 * Model version : 1.523
* Simulink Coder version : 9.0 (R2018b) 24-May-2018 * Simulink Coder version : 9.0 (R2018b) 24-May-2018
* C/C++ source code generated on : Wed Dec 2 07:33:19 2020 * C/C++ source code generated on : Wed Dec 2 09:48:16 2020
* *
* Target selection: ert_shrlib.tlc * Target selection: ert_shrlib.tlc
* Embedded hardware selection: Intel->x86-64 (Windows64) * Embedded hardware selection: Intel->x86-64 (Windows64)
SIL/work/SIL_ert_shrlib_rtw/SIL_private.h
+3 -3
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@@ -5,7 +5,7 @@
* *
* Model version : 1.523 * Model version : 1.523
* Simulink Coder version : 9.0 (R2018b) 24-May-2018 * Simulink Coder version : 9.0 (R2018b) 24-May-2018
* C/C++ source code generated on : Wed Dec 2 07:33:19 2020 * C/C++ source code generated on : Wed Dec 2 09:48:16 2020
* *
* Target selection: ert_shrlib.tlc * Target selection: ert_shrlib.tlc
* Embedded hardware selection: Intel->x86-64 (Windows64) * Embedded hardware selection: Intel->x86-64 (Windows64)
@@ -96,7 +96,7 @@ preprocessor word size checks.
/* Skipping ulong_long/long_long check: insufficient preprocessor integer range. */ /* Skipping ulong_long/long_long check: insufficient preprocessor integer range. */
extern const real_T rtCP_pooled_Y3lCp5zD21tA[6]; extern const real_T rtCP_pooled_Y3lCp5zD21tA[6];
extern const real_T rtCP_pooled_EFcVM5alguKR[6]; extern const real_T rtCP_pooled_EFcVM5alguKR[6];
extern const real_T rtCP_pooled_n9gMyBZ7SBpf[6]; extern const real_T rtCP_pooled_jCajZwqM7jWe[6];
extern const real_T rtCP_pooled_TP0jmN6R2qNh[6]; extern const real_T rtCP_pooled_TP0jmN6R2qNh[6];
extern const real_T rtCP_pooled_FEWufo6vVHrj[9]; extern const real_T rtCP_pooled_FEWufo6vVHrj[9];
extern const real_T rtCP_pooled_B5TQ9jFT4w0p[3]; extern const real_T rtCP_pooled_B5TQ9jFT4w0p[3];
@@ -190,7 +190,7 @@ extern const uint8_T rtCP_pooled_mhMab4fllVU3;
#define rtCP_table1D_CGz_bp01Data rtCP_pooled_EFcVM5alguKR /* Expression: kb3_massbalance_mdl.indep_mass_kg #define rtCP_table1D_CGz_bp01Data rtCP_pooled_EFcVM5alguKR /* Expression: kb3_massbalance_mdl.indep_mass_kg
* Referenced by: '<S98>/table1D_CGz' * Referenced by: '<S98>/table1D_CGz'
*/ */
#define rtCP_table1D_CGy_tableData rtCP_pooled_n9gMyBZ7SBpf /* Expression: kb3_massbalance_mdl.tab_CGy #define rtCP_table1D_CGy_tableData rtCP_pooled_jCajZwqM7jWe /* Expression: kb3_massbalance_mdl.tab_CGy
* Referenced by: '<S98>/table1D_CGy' * Referenced by: '<S98>/table1D_CGy'
*/ */
#define rtCP_table1D_CGy_bp01Data rtCP_pooled_EFcVM5alguKR /* Expression: kb3_massbalance_mdl.indep_mass_kg #define rtCP_table1D_CGy_bp01Data rtCP_pooled_EFcVM5alguKR /* Expression: kb3_massbalance_mdl.indep_mass_kg
SIL/work/SIL_ert_shrlib_rtw/SIL_types.h
+1 -1
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@@ -5,7 +5,7 @@
* *
* Model version : 1.523 * Model version : 1.523
* Simulink Coder version : 9.0 (R2018b) 24-May-2018 * Simulink Coder version : 9.0 (R2018b) 24-May-2018
* C/C++ source code generated on : Wed Dec 2 07:33:19 2020 * C/C++ source code generated on : Wed Dec 2 09:48:16 2020
* *
* Target selection: ert_shrlib.tlc * Target selection: ert_shrlib.tlc
* Embedded hardware selection: Intel->x86-64 (Windows64) * Embedded hardware selection: Intel->x86-64 (Windows64)
SIL/work/SIL_ert_shrlib_rtw/buildInfo.mat
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SIL/work/SIL_ert_shrlib_rtw/rtmodel.h
+1 -1
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@@ -5,7 +5,7 @@
* *
* Model version : 1.523 * Model version : 1.523
* Simulink Coder version : 9.0 (R2018b) 24-May-2018 * Simulink Coder version : 9.0 (R2018b) 24-May-2018
* C/C++ source code generated on : Wed Dec 2 07:33:19 2020 * C/C++ source code generated on : Wed Dec 2 09:48:16 2020
* *
* Target selection: ert_shrlib.tlc * Target selection: ert_shrlib.tlc
* Embedded hardware selection: Intel->x86-64 (Windows64) * Embedded hardware selection: Intel->x86-64 (Windows64)
SIL/work/SIL_win64.dll
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SIL/work/slprj/ert_shrlib/_sharedutils/const_params.c
+4 -1
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@@ -5,7 +5,7 @@
* *
* Model version : 1.523 * Model version : 1.523
* Simulink Coder version : 9.0 (R2018b) 24-May-2018 * Simulink Coder version : 9.0 (R2018b) 24-May-2018
* C source code generated on : Wed Dec 2 07:33:19 2020 * C source code generated on : Wed Dec 2 09:48:16 2020
*/ */
#include "rtwtypes.h" #include "rtwtypes.h"
@@ -3457,6 +3457,9 @@ const real_T rtCP_pooled_i7VqVc2QjHz3[1188] = { 0.014878, 0.017219, 0.019888,
-0.009075, -0.010897, -0.012858, -0.014879, -0.014879, -0.014879, -0.014879, -0.009075, -0.010897, -0.012858, -0.014879, -0.014879, -0.014879, -0.014879,
-0.014879 } ; -0.014879 } ;
extern const real_T rtCP_pooled_jCajZwqM7jWe[6];
const real_T rtCP_pooled_jCajZwqM7jWe[6] = { 0.0, 0.0, 0.0, 0.0, 0.0, 0.0 } ;
extern const real_T rtCP_pooled_lNe8VrimgzRr[9]; extern const real_T rtCP_pooled_lNe8VrimgzRr[9];
const real_T rtCP_pooled_lNe8VrimgzRr[9] = { 0.0, 0.04, 0.5, 1.0, 1.5, 1.83, const real_T rtCP_pooled_lNe8VrimgzRr[9] = { 0.0, 0.04, 0.5, 1.0, 1.5, 1.83,
1.92, 1.94, 2.0 } ; 1.92, 1.94, 2.0 } ;