diff --git a/SIL/work/SIL_ert_shrlib_rtw/SIL.c b/SIL/work/SIL_ert_shrlib_rtw/SIL.c index fa6368d..d60a6d8 100644 --- a/SIL/work/SIL_ert_shrlib_rtw/SIL.c +++ b/SIL/work/SIL_ert_shrlib_rtw/SIL.c @@ -5,7 +5,7 @@ * * Model version : 1.523 * Simulink Coder version : 9.0 (R2018b) 24-May-2018 - * C/C++ source code generated on : Wed Dec 2 07:33:19 2020 + * C/C++ source code generated on : Wed Dec 2 09:48:16 2020 * * Target selection: ert_shrlib.tlc * Embedded hardware selection: Intel->x86-64 (Windows64) @@ -612,7 +612,6 @@ static void SIL_sf_msg_send_cmd(void); static void SIL_update_vert(ENUM_AFCS_VERT in, ENUM_AT in2, ENUM_AFCS_VERT *out, ENUM_AT *out2); static void SIL_parachute(void); -static void SIL_Idle(void); static boolean_T SIL_sf_msg_pop_msgs(void); static void SIL_sf_msg_send_resp(void); static void SIL_sf_msg_send_resp_i(void); @@ -6197,26 +6196,6 @@ static void SIL_parachute(void) } } -/* Function for Chart: '/Chart' */ -static void SIL_Idle(void) -{ - if ((SIL_B.merged.recovery & 1U) != 0U) { - SIL_DW.is_c59_kb3_autopilot = SIL_IN_parachute; - SIL_DW.temporalCounter_i2 = 0U; - SIL_B.recovery_out = 1U; - SIL_DW.is_parachute = SIL_IN_one; - SIL_DW.temporalCounter_i1_fn = 0U; - SIL_B.ch_out = 3U; - SIL_B.peroid_out = 50U; - SIL_B.sw_out = 1U; - } else { - SIL_B.recovery_out = SIL_B.merged.recovery; - SIL_B.ch_out = SIL_B.merged.ccm_ch; - SIL_B.peroid_out = SIL_B.merged.ccm_period; - SIL_B.sw_out = SIL_B.merged.ccm_sw; - } -} - int32_T SIL_pop_c02u1irtbrb(Queue_mavlink_message_t *q, Msg_mavlink_message_t *elementOut) { @@ -18422,7 +18401,21 @@ void SIL_step(void) } else { switch (SIL_DW.is_c59_kb3_autopilot) { case SIL_IN_Idle_o: - SIL_Idle(); + if ((SIL_B.merged.recovery & 1U) != 0U) { + SIL_DW.is_c59_kb3_autopilot = SIL_IN_parachute; + SIL_DW.temporalCounter_i2 = 0U; + SIL_B.recovery_out = 1U; + SIL_DW.is_parachute = SIL_IN_one; + SIL_DW.temporalCounter_i1_fn = 0U; + SIL_B.ch_out = 3U; + SIL_B.peroid_out = 50U; + SIL_B.sw_out = 1U; + } else { + SIL_B.recovery_out = SIL_B.merged.recovery; + SIL_B.ch_out = SIL_B.merged.ccm_ch; + SIL_B.peroid_out = SIL_B.merged.ccm_period; + SIL_B.sw_out = SIL_B.merged.ccm_sw; + } break; case SIL_IN_Idle1: diff --git a/SIL/work/SIL_ert_shrlib_rtw/SIL.h b/SIL/work/SIL_ert_shrlib_rtw/SIL.h index 585903c..da3e4a8 100644 --- a/SIL/work/SIL_ert_shrlib_rtw/SIL.h +++ b/SIL/work/SIL_ert_shrlib_rtw/SIL.h @@ -5,7 +5,7 @@ * * Model version : 1.523 * Simulink Coder version : 9.0 (R2018b) 24-May-2018 - * C/C++ source code generated on : Wed Dec 2 07:33:19 2020 + * C/C++ source code generated on : Wed Dec 2 09:48:16 2020 * * Target selection: ert_shrlib.tlc * Embedded hardware selection: Intel->x86-64 (Windows64) diff --git a/SIL/work/SIL_ert_shrlib_rtw/SIL_capi.c b/SIL/work/SIL_ert_shrlib_rtw/SIL_capi.c index b5bdfaa..56ca3ae 100644 --- a/SIL/work/SIL_ert_shrlib_rtw/SIL_capi.c +++ b/SIL/work/SIL_ert_shrlib_rtw/SIL_capi.c @@ -5,7 +5,7 @@ * * Model version : 1.523 * Simulink Coder version : 9.0 (R2018b) 24-May-2018 - * C/C++ source code generated on : Wed Dec 2 07:33:19 2020 + * C/C++ source code generated on : Wed Dec 2 09:48:16 2020 * * Target selection: ert_shrlib.tlc * Embedded hardware selection: Intel->x86-64 (Windows64) @@ -472,10 +472,10 @@ static rtwCAPI_ModelMappingStaticInfo mmiStatic = { rtElementMap, rtSampleTimeMap, rtDimensionArray }, "float", - { 2018390078U, - 3538475814U, - 307450848U, - 1694129538U }, + { 802743795U, + 3370625247U, + 1938363916U, + 2287030912U }, (NULL), 0, 0 }; diff --git a/SIL/work/SIL_ert_shrlib_rtw/SIL_capi.h b/SIL/work/SIL_ert_shrlib_rtw/SIL_capi.h index e9b10ff..1010c73 100644 --- a/SIL/work/SIL_ert_shrlib_rtw/SIL_capi.h +++ b/SIL/work/SIL_ert_shrlib_rtw/SIL_capi.h @@ -5,7 +5,7 @@ * * Model version : 1.523 * Simulink Coder version : 9.0 (R2018b) 24-May-2018 - * C/C++ source code generated on : Wed Dec 2 07:33:19 2020 + * C/C++ source code generated on : Wed Dec 2 09:48:16 2020 * * Target selection: ert_shrlib.tlc * Embedded hardware selection: Intel->x86-64 (Windows64) diff --git a/SIL/work/SIL_ert_shrlib_rtw/SIL_data.c b/SIL/work/SIL_ert_shrlib_rtw/SIL_data.c index f51cd07..4c5e0bc 100644 --- a/SIL/work/SIL_ert_shrlib_rtw/SIL_data.c +++ b/SIL/work/SIL_ert_shrlib_rtw/SIL_data.c @@ -5,7 +5,7 @@ * * Model version : 1.523 * Simulink Coder version : 9.0 (R2018b) 24-May-2018 - * C/C++ source code generated on : Wed Dec 2 07:33:19 2020 + * C/C++ source code generated on : Wed Dec 2 09:48:16 2020 * * Target selection: ert_shrlib.tlc * Embedded hardware selection: Intel->x86-64 (Windows64) diff --git a/SIL/work/SIL_ert_shrlib_rtw/SIL_private.h b/SIL/work/SIL_ert_shrlib_rtw/SIL_private.h index 33e40c7..bbce6d8 100644 --- a/SIL/work/SIL_ert_shrlib_rtw/SIL_private.h +++ b/SIL/work/SIL_ert_shrlib_rtw/SIL_private.h @@ -5,7 +5,7 @@ * * Model version : 1.523 * Simulink Coder version : 9.0 (R2018b) 24-May-2018 - * C/C++ source code generated on : Wed Dec 2 07:33:19 2020 + * C/C++ source code generated on : Wed Dec 2 09:48:16 2020 * * Target selection: ert_shrlib.tlc * Embedded hardware selection: Intel->x86-64 (Windows64) @@ -96,7 +96,7 @@ preprocessor word size checks. /* Skipping ulong_long/long_long check: insufficient preprocessor integer range. */ extern const real_T rtCP_pooled_Y3lCp5zD21tA[6]; extern const real_T rtCP_pooled_EFcVM5alguKR[6]; -extern const real_T rtCP_pooled_n9gMyBZ7SBpf[6]; +extern const real_T rtCP_pooled_jCajZwqM7jWe[6]; extern const real_T rtCP_pooled_TP0jmN6R2qNh[6]; extern const real_T rtCP_pooled_FEWufo6vVHrj[9]; extern const real_T rtCP_pooled_B5TQ9jFT4w0p[3]; @@ -190,7 +190,7 @@ extern const uint8_T rtCP_pooled_mhMab4fllVU3; #define rtCP_table1D_CGz_bp01Data rtCP_pooled_EFcVM5alguKR /* Expression: kb3_massbalance_mdl.indep_mass_kg * Referenced by: '/table1D_CGz' */ -#define rtCP_table1D_CGy_tableData rtCP_pooled_n9gMyBZ7SBpf /* Expression: kb3_massbalance_mdl.tab_CGy +#define rtCP_table1D_CGy_tableData rtCP_pooled_jCajZwqM7jWe /* Expression: kb3_massbalance_mdl.tab_CGy * Referenced by: '/table1D_CGy' */ #define rtCP_table1D_CGy_bp01Data rtCP_pooled_EFcVM5alguKR /* Expression: kb3_massbalance_mdl.indep_mass_kg diff --git a/SIL/work/SIL_ert_shrlib_rtw/SIL_types.h b/SIL/work/SIL_ert_shrlib_rtw/SIL_types.h index 0850406..3dddc32 100644 --- a/SIL/work/SIL_ert_shrlib_rtw/SIL_types.h +++ b/SIL/work/SIL_ert_shrlib_rtw/SIL_types.h @@ -5,7 +5,7 @@ * * Model version : 1.523 * Simulink Coder version : 9.0 (R2018b) 24-May-2018 - * C/C++ source code generated on : Wed Dec 2 07:33:19 2020 + * C/C++ source code generated on : Wed Dec 2 09:48:16 2020 * * Target selection: ert_shrlib.tlc * Embedded hardware selection: Intel->x86-64 (Windows64) diff --git a/SIL/work/SIL_ert_shrlib_rtw/buildInfo.mat b/SIL/work/SIL_ert_shrlib_rtw/buildInfo.mat index 36abd8b..d7a5b1f 100644 Binary files a/SIL/work/SIL_ert_shrlib_rtw/buildInfo.mat and b/SIL/work/SIL_ert_shrlib_rtw/buildInfo.mat differ diff --git a/SIL/work/SIL_ert_shrlib_rtw/rtmodel.h b/SIL/work/SIL_ert_shrlib_rtw/rtmodel.h index e460d5a..346f04b 100644 --- a/SIL/work/SIL_ert_shrlib_rtw/rtmodel.h +++ b/SIL/work/SIL_ert_shrlib_rtw/rtmodel.h @@ -5,7 +5,7 @@ * * Model version : 1.523 * Simulink Coder version : 9.0 (R2018b) 24-May-2018 - * C/C++ source code generated on : Wed Dec 2 07:33:19 2020 + * C/C++ source code generated on : Wed Dec 2 09:48:16 2020 * * Target selection: ert_shrlib.tlc * Embedded hardware selection: Intel->x86-64 (Windows64) diff --git a/SIL/work/SIL_win64.dll b/SIL/work/SIL_win64.dll index 995fe4e..8b1955f 100644 Binary files a/SIL/work/SIL_win64.dll and b/SIL/work/SIL_win64.dll differ diff --git a/SIL/work/slprj/ert_shrlib/_sharedutils/const_params.c b/SIL/work/slprj/ert_shrlib/_sharedutils/const_params.c index 50b33ec..eef00f2 100644 --- a/SIL/work/slprj/ert_shrlib/_sharedutils/const_params.c +++ b/SIL/work/slprj/ert_shrlib/_sharedutils/const_params.c @@ -5,7 +5,7 @@ * * Model version : 1.523 * Simulink Coder version : 9.0 (R2018b) 24-May-2018 - * C source code generated on : Wed Dec 2 07:33:19 2020 + * C source code generated on : Wed Dec 2 09:48:16 2020 */ #include "rtwtypes.h" @@ -3457,6 +3457,9 @@ const real_T rtCP_pooled_i7VqVc2QjHz3[1188] = { 0.014878, 0.017219, 0.019888, -0.009075, -0.010897, -0.012858, -0.014879, -0.014879, -0.014879, -0.014879, -0.014879 } ; +extern const real_T rtCP_pooled_jCajZwqM7jWe[6]; +const real_T rtCP_pooled_jCajZwqM7jWe[6] = { 0.0, 0.0, 0.0, 0.0, 0.0, 0.0 } ; + extern const real_T rtCP_pooled_lNe8VrimgzRr[9]; const real_T rtCP_pooled_lNe8VrimgzRr[9] = { 0.0, 0.04, 0.5, 1.0, 1.5, 1.83, 1.92, 1.94, 2.0 } ;