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update gencode

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This commit is contained in:
matt
2020-12-02 09:59:07 +08:00
parent 8463e0518d
commit b064e82d9d
11 changed files with 33 additions and 37 deletions
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SIL/work/SIL_ert_shrlib_rtw/SIL_private.h
+3 -3
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@@ -5,7 +5,7 @@
*
* Model version : 1.523
* Simulink Coder version : 9.0 (R2018b) 24-May-2018
* C/C++ source code generated on : Wed Dec 2 07:33:19 2020
* C/C++ source code generated on : Wed Dec 2 09:48:16 2020
*
* Target selection: ert_shrlib.tlc
* Embedded hardware selection: Intel->x86-64 (Windows64)
@@ -96,7 +96,7 @@ preprocessor word size checks.
/* Skipping ulong_long/long_long check: insufficient preprocessor integer range. */
extern const real_T rtCP_pooled_Y3lCp5zD21tA[6];
extern const real_T rtCP_pooled_EFcVM5alguKR[6];
extern const real_T rtCP_pooled_n9gMyBZ7SBpf[6];
extern const real_T rtCP_pooled_jCajZwqM7jWe[6];
extern const real_T rtCP_pooled_TP0jmN6R2qNh[6];
extern const real_T rtCP_pooled_FEWufo6vVHrj[9];
extern const real_T rtCP_pooled_B5TQ9jFT4w0p[3];
@@ -190,7 +190,7 @@ extern const uint8_T rtCP_pooled_mhMab4fllVU3;
#define rtCP_table1D_CGz_bp01Data rtCP_pooled_EFcVM5alguKR /* Expression: kb3_massbalance_mdl.indep_mass_kg
* Referenced by: '<S98>/table1D_CGz'
*/
#define rtCP_table1D_CGy_tableData rtCP_pooled_n9gMyBZ7SBpf /* Expression: kb3_massbalance_mdl.tab_CGy
#define rtCP_table1D_CGy_tableData rtCP_pooled_jCajZwqM7jWe /* Expression: kb3_massbalance_mdl.tab_CGy
* Referenced by: '<S98>/table1D_CGy'
*/
#define rtCP_table1D_CGy_bp01Data rtCP_pooled_EFcVM5alguKR /* Expression: kb3_massbalance_mdl.indep_mass_kg