2023-07-07 10:38:51 +08:00
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/*
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2023-07-08 18:10:03 +08:00
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* File: AFCS_Model_v2_20230705.h
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2023-07-07 10:38:51 +08:00
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*
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2023-07-08 18:10:03 +08:00
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* Code generated for Simulink model 'AFCS_Model_v2_20230705'.
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2023-07-07 10:38:51 +08:00
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*
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2023-07-08 18:10:03 +08:00
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* Model version : 1.876
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2023-07-07 10:38:51 +08:00
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* Simulink Coder version : 9.0 (R2018b) 24-May-2018
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2023-07-08 18:10:03 +08:00
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* C/C++ source code generated on : Wed Jul 5 15:50:46 2023
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2023-07-07 10:38:51 +08:00
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*
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* Target selection: ert.tlc
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* Embedded hardware selection: Intel->x86-64 (Windows64)
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* Code generation objectives: Unspecified
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* Validation result: Not run
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*/
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2023-07-08 18:10:03 +08:00
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#ifndef RTW_HEADER_AFCS_Model_v2_20230705_h_
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#define RTW_HEADER_AFCS_Model_v2_20230705_h_
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2023-07-07 10:38:51 +08:00
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#include <float.h>
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#include <math.h>
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#include <string.h>
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#include "tmwtypes.h"
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/* External inputs (root inport signals with default storage) */
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typedef struct {
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real_T irs_pitch_ang_sel; /* '<Root>/irs_pitch_ang_sel' */
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real_T irs_fpa_sel; /* '<Root>/irs_fpa_sel' */
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real_T irs_roll_ang_sel; /* '<Root>/irs_roll_ang_sel' */
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real_T irs_pitch_rate_sel; /* '<Root>/irs_pitch_rate_sel' */
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real_T irs_inrtl_vert_spd_sel; /* '<Root>/irs_inrtl_vert_spd_sel' */
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real_T irs_gnd_spd_sel; /* '<Root>/irs_gnd_spd_sel' */
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real_T irs_true_hdg_sel; /* '<Root>/irs_true_hdg_sel' */
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real_T irs_true_trk_ang_sel; /* '<Root>/irs_true_trk_ang_sel' */
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real_T irs_longitude_accel_sel; /* '<Root>/irs_longitude_accel_sel' */
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real_T irs_lat_accel_sel; /* '<Root>/irs_lat_accel_sel' */
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real_T irs_norm_accel_sel; /* '<Root>/irs_norm_accel_sel' */
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real_T ra_fltr_ht_sel; /* '<Root>/ra_fltr_ht_sel' */
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real_T cas_vtd; /* '<Root>/cas_vtd' */
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real_T mach_vtd; /* '<Root>/mach_vtd' */
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real_T press_alt_vtd; /* '<Root>/press_alt_vtd' */
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real_T baro_corr_alt_baro_set_1_vtd; /* '<Root>/baro_corr_alt_baro_set_1_vtd' */
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real_T baro_corr_alt_baro_set_2_vtd; /* '<Root>/baro_corr_alt_baro_set_2_vtd' */
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real_T tas_vtd; /* '<Root>/tas_vtd' */
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boolean_T ssu_capt_ap_dcn_priorty; /* '<Root>/ssu_capt_ap_dcn_priorty' */
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boolean_T ssu_fo_ap_dcn_priorty; /* '<Root>/ssu_fo_ap_dcn_priorty' */
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boolean_T fmcp_a_alt_pb_sel; /* '<Root>/fmcp_a_alt_pb_sel' */
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boolean_T fmcp_a_ap_pb_sel; /* '<Root>/fmcp_a_ap_pb_sel' */
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boolean_T fmcp_a_appr_pb_sel; /* '<Root>/fmcp_a_appr_pb_sel' */
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boolean_T fmcp_a_at_pb_sel; /* '<Root>/fmcp_a_at_pb_sel' */
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boolean_T fmcp_a_fd_td_pb_l_sel; /* '<Root>/fmcp_a_fd_td_pb_l_sel' */
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boolean_T fmcp_a_fd_td_pb_r_sel; /* '<Root>/fmcp_a_fd_td_pb_r_sel' */
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boolean_T fmcp_a_flc_pb_sel; /* '<Root>/fmcp_a_flc_pb_sel' */
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boolean_T fmcp_a_hdg_trk_pb_sel; /* '<Root>/fmcp_a_hdg_trk_pb_sel' */
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boolean_T fmcp_a_hdg_trk_sync_pb_sel;/* '<Root>/fmcp_a_hdg_trk_sync_pb_sel' */
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boolean_T fmcp_a_lnav_pb_sel; /* '<Root>/fmcp_a_lnav_pb_sel' */
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boolean_T fmcp_a_plt_side_pb_sel; /* '<Root>/fmcp_a_plt_side_pb_sel' */
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boolean_T fmcp_a_spd_toggle_pb_sel; /* '<Root>/fmcp_a_spd_toggle_pb_sel' */
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boolean_T fmcp_a_vnav_pb_sel; /* '<Root>/fmcp_a_vnav_pb_sel' */
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boolean_T fmcp_a_vs_pb_sel; /* '<Root>/fmcp_a_vs_pb_sel' */
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boolean_T fmcp_b_alt_pb_sel; /* '<Root>/fmcp_b_alt_pb_sel' */
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boolean_T fmcp_b_ap_pb_sel; /* '<Root>/fmcp_b_ap_pb_sel' */
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boolean_T fmcp_b_appr_pb_sel; /* '<Root>/fmcp_b_appr_pb_sel' */
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boolean_T fmcp_b_at_pb_sel; /* '<Root>/fmcp_b_at_pb_sel' */
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boolean_T fmcp_b_fd_td_pb_l_sel; /* '<Root>/fmcp_b_fd_td_pb_l_sel' */
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boolean_T fmcp_b_fd_td_pb_r_sel; /* '<Root>/fmcp_b_fd_td_pb_r_sel' */
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boolean_T fmcp_b_flc_pb_sel; /* '<Root>/fmcp_b_flc_pb_sel' */
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boolean_T fmcp_b_hdg_trk_pb_sel; /* '<Root>/fmcp_b_hdg_trk_pb_sel' */
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boolean_T fmcp_b_hdg_trk_sync_pb_sel;/* '<Root>/fmcp_b_hdg_trk_sync_pb_sel' */
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boolean_T fmcp_b_lnav_pb_sel; /* '<Root>/fmcp_b_lnav_pb_sel' */
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boolean_T fmcp_b_plt_side_pb_sel; /* '<Root>/fmcp_b_plt_side_pb_sel' */
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boolean_T fmcp_b_spd_toggle_pb_sel; /* '<Root>/fmcp_b_spd_toggle_pb_sel' */
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boolean_T fmcp_b_vnav_pb_sel; /* '<Root>/fmcp_b_vnav_pb_sel' */
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boolean_T fmcp_b_vs_pb_sel; /* '<Root>/fmcp_b_vs_pb_sel' */
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int32_T fmcp_a_asel_knob_click_sel; /* '<Root>/fmcp_a_asel_knob_click_sel' */
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int32_T fmcp_b_asel_knob_click_sel; /* '<Root>/fmcp_b_asel_knob_click_sel' */
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int32_T fmcp_a_fpa_vs_knob_click_sel;/* '<Root>/fmcp_a_fpa_vs_knob_click_sel' */
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int32_T fmcp_b_fpa_vs_knob_click_sel;/* '<Root>/fmcp_b_fpa_vs_knob_click_sel' */
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int32_T fmcp_a_hdg_trk_knob_click_sel;/* '<Root>/fmcp_a_hdg_trk_knob_click_sel' */
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int32_T fmcp_b_hdg_trk_knob_click_sel;/* '<Root>/fmcp_b_hdg_trk_knob_click_sel' */
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int32_T fmcp_a_spd_knob_click_sel; /* '<Root>/fmcp_a_spd_knob_click_sel' */
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int32_T fmcp_b_spd_knob_click_sel; /* '<Root>/fmcp_b_spd_knob_click_sel' */
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boolean_T fmcp_a_spd_src_ref_sel; /* '<Root>/fmcp_a_spd_src_ref_sel' */
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boolean_T fmcp_a_hdg_trk_ref_sel; /* '<Root>/fmcp_a_hdg_trk_ref_sel' */
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boolean_T fmcp_b_spd_src_ref_sel; /* '<Root>/fmcp_b_spd_src_ref_sel' */
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boolean_T fmcp_b_hdg_trk_ref_sel; /* '<Root>/fmcp_b_hdg_trk_ref_sel' */
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boolean_T fmcp_a_asel_knob_resol_sel;/* '<Root>/fmcp_a_asel_knob_resol_sel' */
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boolean_T fmcp_b_asel_knob_resol_sel;/* '<Root>/fmcp_b_asel_knob_resol_sel' */
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boolean_T toga_sw_l_sel; /* '<Root>/toga_sw_l_sel' */
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boolean_T toga_sw_r_sel; /* '<Root>/toga_sw_r_sel' */
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boolean_T at_diseng_sw_l_sel; /* '<Root>/at_diseng_sw_l_sel' */
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boolean_T at_diseng_sw_r_sel; /* '<Root>/at_diseng_sw_r_sel' */
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real_T Beta_deg; /* '<Root>/Beta_deg' */
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real_T da_deg; /* '<Root>/da_deg' */
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real_T de_deg; /* '<Root>/de_deg' */
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real_T dr_deg; /* '<Root>/dr_deg' */
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real_T dsplo5_deg; /* '<Root>/dsplo5_deg' */
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real_T dsplo4_deg; /* '<Root>/dsplo4_deg' */
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real_T dsplo3_deg; /* '<Root>/dsplo3_deg' */
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real_T dsplo2_deg; /* '<Root>/dsplo2_deg' */
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real_T dsplo1_deg; /* '<Root>/dsplo1_deg' */
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real_T dspli3_deg; /* '<Root>/dspli3_deg' */
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real_T dspli2_deg; /* '<Root>/dspli2_deg' */
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real_T dspli1_deg; /* '<Root>/dspli1_deg' */
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real_T dspri1_deg; /* '<Root>/dspri1_deg' */
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real_T dspri2_deg; /* '<Root>/dspri2_deg' */
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real_T dspri3_deg; /* '<Root>/dspri3_deg' */
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real_T dspro1_deg; /* '<Root>/dspro1_deg' */
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real_T dspro2_deg; /* '<Root>/dspro2_deg' */
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real_T dspro3_deg; /* '<Root>/dspro3_deg' */
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real_T dspro4_deg; /* '<Root>/dspro4_deg' */
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real_T dspro5_deg; /* '<Root>/dspro5_deg' */
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real_T horizontal_tail_deg; /* '<Root>/horizontal_tail_deg' */
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real_T flap_lever_in; /* '<Root>/flap_lever_in' */
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real_T RefArea_m2; /* '<Root>/RefArea_m2' */
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real_T qbar_Pa; /* '<Root>/qbar_Pa' */
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real_T mass_kg; /* '<Root>/mass_kg' */
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real_T Po_Pa; /* '<Root>/Po_Pa' */
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real_T throttle; /* '<Root>/throttle' */
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2023-07-08 18:10:03 +08:00
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real_T aoa_body_sel; /* '<Root>/aoa_body_sel' */
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2023-08-14 09:20:07 +08:00
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} ExtU_AFCS_Model_v3_20230712_T;
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2023-07-07 10:38:51 +08:00
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/* External outputs (root outports fed by signals with default storage) */
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typedef struct {
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real_T ap_tht_cmd; /* '<Root>/ap_tht_cmd' */
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real_T ap_phi_cmd; /* '<Root>/ap_phi_cmd' */
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real_T fd_roll_bar; /* '<Root>/fd_roll_bar' */
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boolean_T ap_dcn_warn_det; /* '<Root>/ap_dcn_warn_det' */
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real_T throttle_c; /* '<Root>/throttle_c' */
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boolean_T AP_Engage_Request_b; /* '<Root>/AP_Engage_Request_b' */
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boolean_T ap_engaged; /* '<Root>/ap_engaged' */
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boolean_T at_control_mode_armed; /* '<Root>/at_control_mode_armed' */
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uint32_T at_engaged_status; /* '<Root>/at_engaged_status' */
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uint32_T at_control_mode; /* '<Root>/at_control_mode' */
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uint32_T appr_mode_arm; /* '<Root>/appr_mode_arm' */
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uint32_T appr_mode_engaged; /* '<Root>/appr_mode_engaged' */
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uint32_T fd_arm_vert_mode_1; /* '<Root>/fd_arm_vert_mode_1' */
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uint32_T fd_actv_lat_mode; /* '<Root>/fd_actv_lat_mode' */
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uint32_T fd_actv_vert_mode; /* '<Root>/fd_actv_vert_mode' */
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uint32_T fd_arm_lat_mode; /* '<Root>/fd_arm_lat_mode' */
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real_T sel_alt_dspl; /* '<Root>/sel_alt_dspl' */
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real_T sel_vs_dspl; /* '<Root>/sel_vs_dspl' */
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real_T sel_fpa_dspl; /* '<Root>/sel_fpa_dspl' */
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real_T sel_hdg_trk_dspl; /* '<Root>/sel_hdg_trk_dspl' */
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real_T sel_spd_dspl; /* '<Root>/sel_spd_dspl' */
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real_T sel_mach_dspl; /* '<Root>/sel_mach_dspl' */
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real_T fmcp_sel_fpa_vs; /* '<Root>/fmcp_sel_fpa_vs' */
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boolean_T alt_hld_ann; /* '<Root>/alt_hld_ann' */
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boolean_T ap_actv_ann; /* '<Root>/ap_actv_ann' */
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boolean_T appr_actv_ann; /* '<Root>/appr_actv_ann' */
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boolean_T appr_arm_ann; /* '<Root>/appr_arm_ann' */
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boolean_T at_actv_ann; /* '<Root>/at_actv_ann' */
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boolean_T at_arm_ann; /* '<Root>/at_arm_ann' */
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boolean_T flc_ann; /* '<Root>/flc_ann' */
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boolean_T fpa_ann; /* '<Root>/fpa_ann' */
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boolean_T hdg_sel_ann; /* '<Root>/hdg_sel_ann' */
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boolean_T ias_mach_ann; /* '<Root>/ias_mach_ann' */
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boolean_T fd_td_l_ann; /* '<Root>/fd_td_l_ann' */
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boolean_T fd_td_r_ann; /* '<Root>/fd_td_r_ann' */
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boolean_T lnav_actv_ann; /* '<Root>/lnav_actv_ann' */
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boolean_T vnav_actv_ann; /* '<Root>/vnav_actv_ann' */
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boolean_T vs_ann; /* '<Root>/vs_ann' */
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boolean_T lnav_arm_ann; /* '<Root>/lnav_arm_ann' */
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real_T fd_pitch_bar; /* '<Root>/fd_pitch_bar' */
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boolean_T at_engaged; /* '<Root>/at_engaged' */
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real_T loc_devn_sel; /* '<Root>/loc_devn_sel' */
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real_T gs_devn_sel; /* '<Root>/gs_devn_sel' */
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2023-08-14 09:20:07 +08:00
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} ExtY_AFCS_Model_v3_20230712_T;
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/* External inputs (root inport signals with default storage) */
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extern ExtU_AFCS_Model_v3_20230712_T AFCS_Model_v3_20230712_U;
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/* External outputs (root outports fed by signals with default storage) */
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2023-08-14 09:20:07 +08:00
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extern ExtY_AFCS_Model_v3_20230712_T AFCS_Model_v3_20230712_Y;
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/* External data declarations for dependent source files */
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/* Model entry point functions */
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extern void AFCS_Model_v3_20230712_initialize(void);
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extern void AFCS_Model_v3_20230712_step(void);
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2023-07-07 10:38:51 +08:00
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2023-08-14 09:20:07 +08:00
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extern void AFCS_Model_v3_step(
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real_T irs_pitch_ang_sel,
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real_T irs_fpa_sel,
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real_T irs_roll_ang_sel,
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real_T irs_pitch_rate_sel,
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real_T irs_inrtl_vert_spd_sel,
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real_T irs_gnd_spd_sel,
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real_T irs_true_hdg_sel,
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real_T irs_true_trk_ang_sel,
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real_T irs_longitude_accel_sel,
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real_T irs_lat_accel_sel,
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real_T irs_norm_accel_sel,
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real_T ra_fltr_ht_sel,
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real_T cas_vtd,
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real_T mach_vtd,
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real_T press_alt_vtd,
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real_T baro_corr_alt_baro_set_1_vtd,
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real_T baro_corr_alt_baro_set_2_vtd,
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real_T tas_vtd,
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boolean_T ssu_capt_ap_dcn_priorty,
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boolean_T ssu_fo_ap_dcn_priorty,
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boolean_T fmcp_a_alt_pb_sel,
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boolean_T fmcp_a_ap_pb_sel,
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|
|
|
|
boolean_T fmcp_a_appr_pb_sel,
|
|
|
|
|
boolean_T fmcp_a_at_pb_sel,
|
|
|
|
|
boolean_T fmcp_a_fd_td_pb_l_sel,
|
|
|
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|
boolean_T fmcp_a_fd_td_pb_r_sel,
|
|
|
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|
boolean_T fmcp_a_flc_pb_sel,
|
|
|
|
|
boolean_T fmcp_a_hdg_trk_pb_sel,
|
|
|
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|
boolean_T fmcp_a_hdg_trk_sync_pb_sel,
|
|
|
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|
boolean_T fmcp_a_lnav_pb_sel,
|
|
|
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|
boolean_T fmcp_a_plt_side_pb_sel,
|
|
|
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|
boolean_T fmcp_a_spd_toggle_pb_sel,
|
|
|
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|
boolean_T fmcp_a_vnav_pb_sel,
|
|
|
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|
boolean_T fmcp_a_vs_pb_sel,
|
|
|
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|
boolean_T fmcp_b_alt_pb_sel,
|
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|
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|
boolean_T fmcp_b_ap_pb_sel,
|
|
|
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|
boolean_T fmcp_b_appr_pb_sel,
|
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|
boolean_T fmcp_b_at_pb_sel,
|
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|
|
|
boolean_T fmcp_b_fd_td_pb_l_sel,
|
|
|
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|
boolean_T fmcp_b_fd_td_pb_r_sel,
|
|
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|
boolean_T fmcp_b_flc_pb_sel,
|
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boolean_T fmcp_b_hdg_trk_pb_sel,
|
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boolean_T fmcp_b_hdg_trk_sync_pb_sel,
|
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|
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boolean_T fmcp_b_lnav_pb_sel,
|
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|
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boolean_T fmcp_b_plt_side_pb_sel,
|
|
|
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|
boolean_T fmcp_b_spd_toggle_pb_sel,
|
|
|
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|
boolean_T fmcp_b_vnav_pb_sel,
|
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|
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|
boolean_T fmcp_b_vs_pb_sel,
|
|
|
|
|
int32_T fmcp_a_asel_knob_click_sel,
|
|
|
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|
int32_T fmcp_b_asel_knob_click_sel,
|
|
|
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|
int32_T fmcp_a_fpa_vs_knob_click_sel,
|
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int32_T fmcp_b_fpa_vs_knob_click_sel,
|
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int32_T fmcp_a_hdg_trk_knob_click_sel,
|
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|
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int32_T fmcp_b_hdg_trk_knob_click_sel,
|
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int32_T fmcp_a_spd_knob_click_sel,
|
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int32_T fmcp_b_spd_knob_click_sel,
|
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|
boolean_T fmcp_a_spd_src_ref_sel,
|
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|
boolean_T fmcp_a_hdg_trk_ref_sel,
|
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boolean_T fmcp_b_spd_src_ref_sel,
|
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boolean_T fmcp_b_hdg_trk_ref_sel,
|
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boolean_T fmcp_a_asel_knob_resol_sel,
|
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|
boolean_T fmcp_b_asel_knob_resol_sel,
|
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|
boolean_T toga_sw_l_sel,
|
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|
boolean_T toga_sw_r_sel,
|
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|
boolean_T at_diseng_sw_l_sel,
|
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|
boolean_T at_diseng_sw_r_sel,
|
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|
|
|
real_T Beta_deg,
|
|
|
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|
real_T da_deg,
|
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|
|
|
real_T de_deg,
|
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|
|
|
real_T dr_deg,
|
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|
|
|
real_T dsplo5_deg,
|
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|
|
|
real_T dsplo4_deg,
|
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|
|
|
real_T dsplo3_deg,
|
|
|
|
|
real_T dsplo2_deg,
|
|
|
|
|
real_T dsplo1_deg,
|
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|
|
|
real_T dspli3_deg,
|
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|
real_T dspli2_deg,
|
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|
|
real_T dspli1_deg,
|
|
|
|
|
real_T dspri1_deg,
|
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|
|
|
real_T dspri2_deg,
|
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|
|
|
real_T dspri3_deg,
|
|
|
|
|
real_T dspro1_deg,
|
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|
|
|
real_T dspro2_deg,
|
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|
|
|
real_T dspro3_deg,
|
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|
|
real_T dspro4_deg,
|
|
|
|
|
real_T dspro5_deg,
|
|
|
|
|
real_T horizontal_tail_deg,
|
|
|
|
|
real_T flap_lever_in,
|
|
|
|
|
real_T RefArea_m2,
|
|
|
|
|
real_T qbar_Pa,
|
|
|
|
|
real_T mass_kg,
|
|
|
|
|
real_T Po_Pa,
|
|
|
|
|
real_T throttle,
|
2023-07-08 18:10:03 +08:00
|
|
|
real_T aoa_body_sel,
|
|
|
|
|
real_T *ap_tht_cmd,
|
2023-07-07 10:38:51 +08:00
|
|
|
real_T *ap_phi_cmd,
|
|
|
|
|
real_T *fd_roll_bar,
|
|
|
|
|
boolean_T *ap_dcn_warn_det,
|
|
|
|
|
real_T *throttle_c,
|
|
|
|
|
boolean_T *AP_Engage_Request_b,
|
|
|
|
|
boolean_T *ap_engaged,
|
|
|
|
|
boolean_T *at_control_mode_armed,
|
|
|
|
|
uint32_T *at_engaged_status,
|
|
|
|
|
uint32_T *at_control_mode,
|
|
|
|
|
uint32_T *appr_mode_arm,
|
|
|
|
|
uint32_T *appr_mode_engaged,
|
|
|
|
|
uint32_T *fd_arm_vert_mode_1,
|
|
|
|
|
uint32_T *fd_actv_lat_mode,
|
|
|
|
|
uint32_T *fd_actv_vert_mode,
|
|
|
|
|
uint32_T *fd_arm_lat_mode,
|
|
|
|
|
real_T *sel_alt_dspl,
|
|
|
|
|
real_T *sel_vs_dspl,
|
|
|
|
|
real_T *sel_fpa_dspl,
|
|
|
|
|
real_T *sel_hdg_trk_dspl,
|
|
|
|
|
real_T *sel_spd_dspl,
|
|
|
|
|
real_T *sel_mach_dspl,
|
|
|
|
|
real_T *fmcp_sel_fpa_vs,
|
|
|
|
|
boolean_T *alt_hld_ann,
|
|
|
|
|
boolean_T *ap_actv_ann,
|
|
|
|
|
boolean_T *appr_actv_ann,
|
|
|
|
|
boolean_T *appr_arm_ann,
|
|
|
|
|
boolean_T *at_actv_ann,
|
|
|
|
|
boolean_T *at_arm_ann,
|
|
|
|
|
boolean_T *flc_ann,
|
|
|
|
|
boolean_T *fpa_ann,
|
|
|
|
|
boolean_T *hdg_sel_ann,
|
|
|
|
|
boolean_T *ias_mach_ann,
|
|
|
|
|
boolean_T *fd_td_l_ann,
|
|
|
|
|
boolean_T *fd_td_r_ann,
|
|
|
|
|
boolean_T *lnav_actv_ann,
|
|
|
|
|
boolean_T *vnav_actv_ann,
|
|
|
|
|
boolean_T *vs_ann,
|
|
|
|
|
boolean_T *lnav_arm_ann,
|
|
|
|
|
real_T *fd_pitch_bar,
|
|
|
|
|
boolean_T *at_engaged,
|
|
|
|
|
real_T *loc_devn_sel,
|
|
|
|
|
real_T *gs_devn_sel
|
|
|
|
|
);
|
|
|
|
|
|
|
|
|
|
|
2023-07-08 18:10:03 +08:00
|
|
|
#endif /* RTW_HEADER_AFCS_Model_v2_20230705_h_ */
|
2023-07-07 10:38:51 +08:00
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* File trailer for generated code.
|
|
|
|
|
*
|
|
|
|
|
* [EOF]
|
|
|
|
|
*/
|
2023-07-08 18:10:03 +08:00
|
|
|
|
