133 lines
3.3 KiB
C
133 lines
3.3 KiB
C
#include "RAMTRON.h"
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#include <stdio.h>
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// register numbers
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#define RAMTRON_RDID 0x9f
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#define RAMTRON_READ 0x03
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#define RAMTRON_RDSR 0x05
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#define RAMTRON_WREN 0x06
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#define RAMTRON_WRITE 0x02
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struct ramtron_id {
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uint8_t id1, id2;
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uint16_t size_kbyte;
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uint8_t addrlen;
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};
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/*
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list of supported devices. Thanks to NuttX ramtron driver
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*/
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static const struct ramtron_id ramtron_ids[] = { { 0x21, 0x00, 16, 2 }, // FM25V01
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{ 0x21, 0x08, 16, 2 }, // FM25V01A
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{ 0x22, 0x00, 32, 2 }, // FM25V02
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{ 0x22, 0x08, 32, 2 }, // FM25V02A
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{ 0x22, 0x01, 32, 2 }, // FM25VN02
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{ 0x23, 0x00, 64, 2 }, // FM25V05
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{ 0x23, 0x01, 64, 2 }, // FM25VN05
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{ 0x24, 0x00, 128, 3 }, // FM25V10
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{ 0x24, 0x01, 128, 3 }, // FM25VN10
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{ 0x25, 0x08, 256, 3 }, // FM25V20A
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{ 0x26, 0x08, 512, 3 }, // CY15B104Q
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{ 0x27, 0x03, 128, 3 }, // MB85RS1MT
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{ 0x05, 0x09, 32, 3 }, // B85RS256B
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{ 0x25, 0x00, 256, 3 }, // FM25V20GL
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};
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uint32_t RAMTRON_size(RAMTRON *fram) {
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return ramtron_ids[fram->id].size_kbyte * 1024UL;
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}
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// initialise the driver
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int RAMTRON_init(RAMTRON *fram, SPI_DEV_t *dev) {
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if (!dev) {
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return -1;
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}
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fram->dev = dev;
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SPI_DEV_begin(fram->dev, -1);
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SPI_DEV_select(fram->dev);
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struct rdid {
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uint8_t manufacturer[6];
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uint8_t memory;
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uint8_t id1;
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uint8_t id2;
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} rdid;
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if (!SPI_DEV_read_registers(fram->dev, RAMTRON_RDID, (uint8_t*) &rdid,
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sizeof(rdid))) {
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SPI_DEV_end(fram->dev);
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SPI_DEV_unselect(fram->dev);
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return -2;
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}
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SPI_DEV_unselect(fram->dev);
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SPI_DEV_end(fram->dev);
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for (uint8_t i = 0; i < sizeof(ramtron_ids)/sizeof(struct ramtron_id); i++) {
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if (ramtron_ids[i].id1 == rdid.id1 && ramtron_ids[i].id2 == rdid.id2) {
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fram->id = i;
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return 0;
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}
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}
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printf("Unknown RAMTRON manufacturer=%02x memory=%02x id1=%02x id2=%02x\n",
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rdid.manufacturer[0], rdid.memory, rdid.id1, rdid.id2);
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return -3;
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}
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/*
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send a command and offset
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*/
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static void send_offset(RAMTRON *fram, uint8_t cmd, uint32_t offset) {
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if (ramtron_ids[fram->id].addrlen == 3) {
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uint8_t b[4] = { cmd, (uint8_t) ((offset >> 16) & 0xFF),
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(uint8_t) ((offset >> 8) & 0xFF), (uint8_t) (offset & 0xFF) };
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SPI_DEV_transfer(fram->dev, b, sizeof(b), NULL, 0, 2);
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} else /* len 2 */{
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uint8_t b[3] = { cmd, (uint8_t) ((offset >> 8) & 0xFF),
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(uint8_t) (offset & 0xFF) };
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SPI_DEV_transfer(fram->dev, b, sizeof(b), NULL, 0, 2);
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}
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}
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// read from device
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bool RAMTRON_read(RAMTRON *fram, uint32_t offset, uint8_t *buf, uint32_t size) {
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const uint8_t maxread = 128;
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while (size > maxread) {
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if (!RAMTRON_read(fram, offset, buf, maxread)) {
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return false;
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}
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offset += maxread;
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buf += maxread;
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size -= maxread;
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}
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SPI_DEV_begin(fram->dev, 10);
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SPI_DEV_select(fram->dev);
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send_offset(fram, RAMTRON_READ, offset);
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// get data
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SPI_DEV_transfer(fram->dev, NULL, 0, buf, size, 10);
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SPI_DEV_unselect(fram->dev);
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SPI_DEV_end(fram->dev);
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return true;
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}
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// write to device
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bool RAMTRON_write(RAMTRON *fram, uint32_t offset, uint8_t *buf, uint32_t size) {
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SPI_DEV_begin(fram->dev, 10);
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// write enable
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uint8_t r = RAMTRON_WREN;
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SPI_DEV_select(fram->dev);
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SPI_DEV_transfer(fram->dev, &r, 1, NULL, 0, 1);
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SPI_DEV_unselect(fram->dev);
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SPI_DEV_select(fram->dev);
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send_offset(fram, RAMTRON_WRITE, offset);
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SPI_DEV_transfer(fram->dev, buf, size, NULL, 0, 1);
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SPI_DEV_unselect(fram->dev);
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SPI_DEV_end(fram->dev);
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return true;
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}
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