hm
b49c9ab0c6
完整实现了以下模块： - 系统数据总线(sys_data_bus)模块间通信 - UART/USART/LPUART驱动 + RS485半双工 - I2C驱动(AS5600角度传感器 + AT24C02 EEPROM) - Modbus RTU从站协议 - 步进电机微步进控制(正弦/余弦换相+S曲线加减速) - 到位开关驱动(DI_MIN/DI_MAX) - PGA+ADC电流检测 - 系统监控任务(内存/串口/传感器/任务状态) - LED/Key外设驱动 - 基于CMake + arm-none-eabi-gcc构建系统
645 lines
24 KiB
C
645 lines
24 KiB
C
#ifndef __PY32MD530_H__
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#define __PY32MD530_H__
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <stdint.h>
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#include "core_cm0plus.h"
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#define __PY32MD530_H_VERSION 0x0100U
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#define FLASH_BASE 0x08000000UL
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#define SRAM_BASE 0x20000000UL
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#define PERIPH_BASE 0x40000000UL
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#define APB1PERIPH_BASE PERIPH_BASE
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#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000UL)
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#define AHB1PERIPH_BASE (PERIPH_BASE + 0x20000UL)
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#define AHB2PERIPH_BASE (PERIPH_BASE + 0x200000UL)
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#define GPIOA_BASE (AHB2PERIPH_BASE + 0x00000000UL)
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#define GPIOB_BASE (AHB2PERIPH_BASE + 0x00000400UL)
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#define GPIOC_BASE (AHB2PERIPH_BASE + 0x00000800UL)
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#define GPIOD_BASE (AHB2PERIPH_BASE + 0x00000C00UL)
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#define GPIOF_BASE (AHB2PERIPH_BASE + 0x00001400UL)
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#define RCC_BASE (AHB1PERIPH_BASE + 0x00001000UL)
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#define USART1_BASE (APB2PERIPH_BASE + 0x3800UL)
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#define UART1_BASE (APB1PERIPH_BASE + 0x4400UL)
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#define LPUART1_BASE (APB1PERIPH_BASE + 0x4800UL)
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#define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL)
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#define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL)
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#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00UL)
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#define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL)
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#define TIM14_BASE (APB1PERIPH_BASE + 0x2000UL)
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#define TIM16_BASE (APB1PERIPH_BASE + 0x2800UL)
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#define TIM17_BASE (APB1PERIPH_BASE + 0x2C00UL)
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#define LPTIM_BASE (APB1PERIPH_BASE + 0x7C00UL)
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#define ADC1_BASE (APB2PERIPH_BASE + 0x2400UL)
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#define DMA1_BASE (AHB1PERIPH_BASE + 0x00000UL)
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#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL)
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#define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL)
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#define RTC_BASE (APB1PERIPH_BASE + 0x2800UL)
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#define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000UL)
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#define EXTI_BASE (APB2PERIPH_BASE + 0x0400UL)
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#define COMP_BASE (APB2PERIPH_BASE + 0x0200UL)
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#define FLASH_SIZE 0x00010000UL
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#define SRAM_SIZE 0x00002000UL
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typedef struct {
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__IOM uint32_t MODER;
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__IOM uint32_t OTYPER;
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__IOM uint32_t OSPEEDR;
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__IOM uint32_t PUPDR;
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__IM uint32_t IDR;
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__IOM uint32_t ODR;
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__IOM uint32_t BSRR;
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__IOM uint32_t LCKR;
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__IOM uint32_t AFRL;
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__IOM uint32_t AFRH;
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__IOM uint32_t BRR;
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} GPIO_TypeDef;
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typedef struct {
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__IOM uint32_t CR;
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__IOM uint32_t CFGR;
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__IOM uint32_t CIR;
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__IOM uint32_t APB2RSTR;
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__IOM uint32_t APB1RSTR;
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__IOM uint32_t AHBENR;
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__IOM uint32_t APB2ENR;
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__IOM uint32_t APB1ENR;
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__IOM uint32_t BDCR;
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__IOM uint32_t CSR;
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__IOM uint32_t AHBRSTR;
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__IOM uint32_t CFGR2;
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__IOM uint32_t CFGR3;
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} RCC_TypeDef;
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typedef struct {
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__IOM uint32_t SR;
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__IOM uint32_t DR;
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__IOM uint32_t BRR;
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__IOM uint32_t CR1;
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__IOM uint32_t CR2;
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__IOM uint32_t CR3;
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__IOM uint32_t GTPR;
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} USART_TypeDef;
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typedef struct {
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__IOM uint32_t ISR;
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__IOM uint32_t DR;
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__IOM uint32_t BRR;
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__IOM uint32_t CR1;
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__IOM uint32_t CR2;
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__IOM uint32_t CR3;
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__IOM uint32_t CR4;
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} LPUART_TypeDef;
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typedef struct {
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__IOM uint32_t CR1;
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__IOM uint32_t CR2;
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__IOM uint32_t OAR1;
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__IOM uint32_t OAR2;
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__IOM uint32_t TIMINGR;
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__IOM uint32_t TIMEOUTR;
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__IOM uint32_t ISR;
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__IOM uint32_t ICR;
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__IOM uint32_t PECR;
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__IOM uint32_t RXDR;
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__IOM uint32_t TXDR;
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} I2C_TypeDef;
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typedef struct {
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__IOM uint32_t CR1;
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__IOM uint32_t CR2;
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__IOM uint32_t SMCR;
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__IOM uint32_t DIER;
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__IOM uint32_t SR;
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__IOM uint32_t EGR;
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__IOM uint32_t CCMR1;
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__IOM uint32_t CCMR2;
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__IOM uint32_t CCER;
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__IOM uint32_t CNT;
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__IOM uint32_t PSC;
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__IOM uint32_t ARR;
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uint32_t RESERVED0;
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__IOM uint32_t CCR1;
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__IOM uint32_t CCR2;
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__IOM uint32_t CCR3;
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__IOM uint32_t CCR4;
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uint32_t RESERVED1;
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__IOM uint32_t DCR;
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__IOM uint32_t DMAR;
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__IOM uint32_t OR1;
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__IOM uint32_t OR2;
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} TIM_TypeDef;
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typedef struct {
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__IOM uint32_t CR1;
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__IOM uint32_t CR2;
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__IOM uint32_t CFGR;
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__IOM uint32_t SMCR;
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__IOM uint32_t DIER;
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__IOM uint32_t SR;
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__IOM uint32_t EGR;
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__IOM uint32_t CCMR1;
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__IOM uint32_t CCMR2;
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__IOM uint32_t CCER;
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__IOM uint32_t CNT;
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__IOM uint32_t PSC;
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__IOM uint32_t ARR;
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__IOM uint32_t RCR;
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__IOM uint32_t CCR1;
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__IOM uint32_t CCR2;
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__IOM uint32_t CCR3;
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__IOM uint32_t CCR4;
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__IOM uint32_t BDTR;
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__IOM uint32_t DCR;
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__IOM uint32_t DMAR;
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__IOM uint32_t OR1;
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__IOM uint32_t CCMR3;
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__IOM uint32_t CCR5;
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__IOM uint32_t CCR6;
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__IOM uint32_t OR2;
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__IOM uint32_t OR3;
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} TIM1_TypeDef;
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typedef struct {
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__IOM uint32_t ISR;
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__IOM uint32_t IER;
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__IOM uint32_t CR;
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__IOM uint32_t CFGR1;
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__IOM uint32_t CFGR2;
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__IOM uint32_t SMPR1;
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__IOM uint32_t SMPR2;
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__IOM uint32_t TR1;
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__IOM uint32_t TR2;
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__IOM uint32_t CHSMPR1;
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__IOM uint32_t CHSMPR2;
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__IOM uint32_t CHDR1;
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__IOM uint32_t CHDR2;
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__IOM uint32_t CHDR3;
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__IOM uint32_t CHDR4;
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__IOM uint32_t CHDR5;
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__IOM uint32_t CHDR6;
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__IOM uint32_t CHDR7;
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} ADC_TypeDef;
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typedef struct {
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__IOM uint32_t CCR;
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__IOM uint32_t CNDTR;
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__IOM uint32_t CPAR;
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__IOM uint32_t CMAR;
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} DMA_Channel_TypeDef;
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typedef struct {
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__IOM uint32_t ISR;
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__IOM uint32_t IFCR;
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} DMA_TypeDef;
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typedef struct {
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__IOM uint32_t CR;
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__IOM uint32_t CFGR;
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__IOM uint32_t CFG2;
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__IOM uint32_t EXTICR[4];
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__IOM uint32_t CFG3;
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} SYSCFG_TypeDef;
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typedef struct {
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__IOM uint32_t IMR;
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__IOM uint32_t EMR;
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__IOM uint32_t RTSR;
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__IOM uint32_t FTSR;
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__IOM uint32_t SWIER;
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__IOM uint32_t PR;
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} EXTI_TypeDef;
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typedef struct {
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__IOM uint32_t KR;
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__IOM uint32_t PR;
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__IOM uint32_t RLR;
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__IOM uint32_t SR;
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} IWDG_TypeDef;
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typedef struct {
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__IOM uint32_t CR;
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__IOM uint32_t CFR;
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__IOM uint32_t SR;
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} WWDG_TypeDef;
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typedef struct {
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__IOM uint32_t TR;
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__IOM uint32_t DR;
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__IOM uint32_t CR;
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__IOM uint32_t ISR;
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__IOM uint32_t PRER;
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__IOM uint32_t WUTR;
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__IOM uint32_t ALRMAR;
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__IOM uint32_t ALRMBR;
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__IOM uint32_t WPR;
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__IOM uint32_t SSR;
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__IOM uint32_t SHIFTR;
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__IOM uint32_t TSTR;
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__IOM uint32_t TSDR;
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__IOM uint32_t TSSSR;
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__IOM uint32_t CALR;
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__IOM uint32_t TAMPCR;
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__IOM uint32_t ALRMASSR;
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__IOM uint32_t ALRMBSSR;
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__IOM uint32_t OR;
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} RTC_TypeDef;
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typedef struct {
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__IOM uint32_t CR1;
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__IOM uint32_t CR2;
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__IOM uint32_t CFGR1;
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__IOM uint32_t CFGR2;
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__IOM uint32_t BRR;
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__IOM uint32_t RESERVED0;
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__IOM uint32_t DIER;
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__IOM uint32_t SR;
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__IOM uint32_t ICFR;
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__IOM uint32_t IER;
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} SPI_TypeDef;
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typedef struct {
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__IOM uint32_t CR;
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__IOM uint32_t CSR;
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} COMP_TypeDef;
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#define GPIOA ((GPIO_TypeDef *)GPIOA_BASE)
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#define GPIOB ((GPIO_TypeDef *)GPIOB_BASE)
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#define GPIOC ((GPIO_TypeDef *)GPIOC_BASE)
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#define GPIOD ((GPIO_TypeDef *)GPIOD_BASE)
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#define GPIOF ((GPIO_TypeDef *)GPIOF_BASE)
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#define RCC ((RCC_TypeDef *)RCC_BASE)
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#define USART1 ((USART_TypeDef *)USART1_BASE)
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#define UART1 ((USART_TypeDef *)UART1_BASE)
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#define LPUART1 ((LPUART_TypeDef *)LPUART1_BASE)
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#define I2C1 ((I2C_TypeDef *)I2C1_BASE)
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#define SPI1 ((SPI_TypeDef *)SPI1_BASE)
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#define TIM1 ((TIM1_TypeDef *)TIM1_BASE)
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#define TIM3 ((TIM_TypeDef *)TIM3_BASE)
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#define TIM14 ((TIM_TypeDef *)TIM14_BASE)
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#define TIM16 ((TIM_TypeDef *)TIM16_BASE)
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#define TIM17 ((TIM_TypeDef *)TIM17_BASE)
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#define LPTIM ((TIM_TypeDef *)LPTIM_BASE)
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#define ADC1 ((ADC_TypeDef *)ADC1_BASE)
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#define DMA1_Channel1 ((DMA_Channel_TypeDef *)(DMA1_BASE + 0x08))
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#define DMA1_Channel2 ((DMA_Channel_TypeDef *)(DMA1_BASE + 0x1C))
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#define DMA1_Channel3 ((DMA_Channel_TypeDef *)(DMA1_BASE + 0x30))
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#define DMA1 ((DMA_TypeDef *)DMA1_BASE)
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#define SYSCFG ((SYSCFG_TypeDef *)SYSCFG_BASE)
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#define EXTI ((EXTI_TypeDef *)EXTI_BASE)
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#define COMP ((COMP_TypeDef *)COMP_BASE)
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#define IWDG ((IWDG_TypeDef *)IWDG_BASE)
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#define WWDG ((WWDG_TypeDef *)WWDG_BASE)
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#define RTC ((RTC_TypeDef *)RTC_BASE)
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#define GPIO_MODER_MODE0_Pos 0U
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#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos)
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#define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos)
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#define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos)
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#define GPIO_OTYPER_OT0_Pos 0U
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#define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos)
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#define GPIO_OTYPER_OT0_0 (0x1UL << GPIO_OTYPER_OT0_Pos)
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#define GPIO_OSPEEDR_OSPEED0_Pos 0U
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#define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)
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#define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)
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#define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)
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#define GPIO_PUPDR_PUPD0_Pos 0U
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#define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos)
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#define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos)
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#define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos)
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#define GPIO_BSRR_BS0_Pos 0U
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#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos)
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#define GPIO_BSRR_BR0_Pos 16U
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#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos)
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#define RCC_AHBENR_GPIOAEN_Pos 17U
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#define RCC_AHBENR_GPIOAEN_Msk (0x1UL << RCC_AHBENR_GPIOAEN_Pos)
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#define RCC_AHBENR_GPIOAEN RCC_AHBENR_GPIOAEN_Msk
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#define RCC_AHBENR_GPIOBEN_Pos 18U
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#define RCC_AHBENR_GPIOBEN_Msk (0x1UL << RCC_AHBENR_GPIOBEN_Pos)
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#define RCC_AHBENR_GPIOBEN RCC_AHBENR_GPIOBEN_Msk
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#define RCC_AHBENR_GPIOCEN_Pos 19U
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#define RCC_AHBENR_GPIOCEN_Msk (0x1UL << RCC_AHBENR_GPIOCEN_Pos)
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#define RCC_AHBENR_GPIOCEN RCC_AHBENR_GPIOCEN_Msk
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#define RCC_AHBENR_GPIOFEN_Pos 22U
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#define RCC_AHBENR_GPIOFEN_Msk (0x1UL << RCC_AHBENR_GPIOFEN_Pos)
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#define RCC_AHBENR_GPIOFEN RCC_AHBENR_GPIOFEN_Msk
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#define RCC_AHBENR_DMAEN_Pos 0U
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#define RCC_AHBENR_DMAEN_Msk (0x1UL << RCC_AHBENR_DMAEN_Pos)
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#define RCC_AHBENR_DMAEN RCC_AHBENR_DMAEN_Msk
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#define RCC_APB2ENR_USART1EN_Pos 14U
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#define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos)
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#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
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#define RCC_APB2ENR_SPI1EN_Pos 12U
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#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos)
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#define RCC_APB2ENR_TIM1EN_Pos 11U
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#define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos)
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#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
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#define RCC_APB2ENR_SYSCFGEN_Pos 0U
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#define RCC_APB2ENR_SYSCFGEN_Msk (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos)
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#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk
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#define RCC_APB2ENR_ADCEN_Pos 9U
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#define RCC_APB2ENR_ADCEN_Msk (0x1UL << RCC_APB2ENR_ADCEN_Pos)
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#define RCC_APB2ENR_ADCEN RCC_APB2ENR_ADCEN_Msk
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#define RCC_APB1ENR_TIM3EN_Pos 1U
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#define RCC_APB1ENR_TIM3EN_Msk (0x1UL << RCC_APB1ENR_TIM3EN_Pos)
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#define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk
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#define RCC_APB1ENR_TIM14EN_Pos 8U
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#define RCC_APB1ENR_TIM14EN_Msk (0x1UL << RCC_APB1ENR_TIM14EN_Pos)
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#define RCC_APB1ENR_TIM14EN RCC_APB1ENR_TIM14EN_Msk
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#define RCC_APB1ENR_UART1EN_Pos 18U
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#define RCC_APB1ENR_UART1EN_Msk (0x1UL << RCC_APB1ENR_UART1EN_Pos)
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#define RCC_APB1ENR_UART1EN RCC_APB1ENR_UART1EN_Msk
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#define RCC_APB1ENR_LPUART1EN_Pos 19U
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#define RCC_APB1ENR_LPUART1EN_Msk (0x1UL << RCC_APB1ENR_LPUART1EN_Pos)
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#define RCC_APB1ENR_LPUART1EN RCC_APB1ENR_LPUART1EN_Msk
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#define RCC_APB1ENR_I2C1EN_Pos 21U
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#define RCC_APB1ENR_I2C1EN_Msk (0x1UL << RCC_APB1ENR_I2C1EN_Pos)
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#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk
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#define RCC_APB1ENR_LPTIMEN_Pos 31U
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#define RCC_APB1ENR_LPTIMEN_Msk (0x1UL << RCC_APB1ENR_LPTIMEN_Pos)
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#define RCC_APB1ENR_PWREN_Pos 28U
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#define RCC_APB1ENR_PWREN_Msk (0x1UL << RCC_APB1ENR_PWREN_Pos)
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#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk
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/* RCC CR register bit definitions */
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#define RCC_CR_HSION_Pos 0U
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#define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos)
|
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#define RCC_CR_HSION RCC_CR_HSION_Msk
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#define RCC_CR_HSIRDY_Pos 1U
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#define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos)
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#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk
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#define RCC_CR_HSITRIM_Pos 3U
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#define RCC_CR_HSITRIM_Msk (0x1FUL << RCC_CR_HSITRIM_Pos)
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#define RCC_CR_HSICAL_Pos 8U
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#define RCC_CR_HSICAL_Msk (0xFFUL << RCC_CR_HSICAL_Pos)
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#define RCC_CR_HSEON_Pos 16U
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#define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos)
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#define RCC_CR_HSERDY_Pos 17U
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#define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos)
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#define RCC_CR_PLLON_Pos 24U
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#define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos)
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#define RCC_CR_PLLON RCC_CR_PLLON_Msk
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#define RCC_CR_PLLRDY_Pos 25U
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#define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos)
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#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk
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/* RCC CFGR register bit definitions */
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#define RCC_CFGR_SW_Pos 0U
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#define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos)
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#define RCC_CFGR_SW RCC_CFGR_SW_Msk
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#define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos)
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#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos)
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#define RCC_CFGR_SW_HSI (0x0UL << RCC_CFGR_SW_Pos)
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#define RCC_CFGR_SW_HSE (0x1UL << RCC_CFGR_SW_Pos)
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#define RCC_CFGR_SW_PLL (0x2UL << RCC_CFGR_SW_Pos)
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#define RCC_CFGR_SWS_Pos 2U
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#define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos)
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#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk
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#define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos)
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#define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos)
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#define RCC_CFGR_SWS_HSI (0x0UL << RCC_CFGR_SWS_Pos)
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#define RCC_CFGR_SWS_HSE (0x1UL << RCC_CFGR_SWS_Pos)
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#define RCC_CFGR_SWS_PLL (0x2UL << RCC_CFGR_SWS_Pos)
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#define RCC_CFGR_HPRE_Pos 4U
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#define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos)
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#define RCC_CFGR_PPRE_Pos 8U
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#define RCC_CFGR_PPRE_Msk (0x7UL << RCC_CFGR_PPRE_Pos)
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#define RCC_CFGR_PLLSRC_Pos 16U
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#define RCC_CFGR_PLLSRC_Msk (0x1UL << RCC_CFGR_PLLSRC_Pos)
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#define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk
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#define RCC_CFGR_PLLXTPRE_Pos 17U
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#define RCC_CFGR_PLLXTPRE_Msk (0x1UL << RCC_CFGR_PLLXTPRE_Pos)
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|
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/* RCC CFGR2 register bit definitions */
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#define RCC_CFGR2_PLLMUL_Pos 0U
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#define RCC_CFGR2_PLLMUL_Msk (0xFUL << RCC_CFGR2_PLLMUL_Pos)
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#define RCC_CFGR2_PLLMUL RCC_CFGR2_PLLMUL_Msk
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#define RCC_CFGR2_PLLMUL2 (0x0UL << RCC_CFGR2_PLLMUL_Pos)
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#define RCC_CFGR2_PLLMUL3 (0x1UL << RCC_CFGR2_PLLMUL_Pos)
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#define RCC_CFGR2_PLLMUL4 (0x2UL << RCC_CFGR2_PLLMUL_Pos)
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#define RCC_CFGR2_PLLMUL5 (0x3UL << RCC_CFGR2_PLLMUL_Pos)
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#define RCC_CFGR2_PLLMUL6 (0x4UL << RCC_CFGR2_PLLMUL_Pos)
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#define RCC_CFGR2_PLLMUL7 (0x5UL << RCC_CFGR2_PLLMUL_Pos)
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#define RCC_CFGR2_PLLMUL8 (0x6UL << RCC_CFGR2_PLLMUL_Pos)
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#define RCC_CFGR2_PLLMUL9 (0x7UL << RCC_CFGR2_PLLMUL_Pos)
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#define RCC_CFGR2_PLLMUL10 (0x8UL << RCC_CFGR2_PLLMUL_Pos)
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#define RCC_CFGR2_PLLMUL11 (0x9UL << RCC_CFGR2_PLLMUL_Pos)
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#define RCC_CFGR2_PLLMUL12 (0xAUL << RCC_CFGR2_PLLMUL_Pos)
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#define RCC_CFGR2_PLLMUL13 (0xBUL << RCC_CFGR2_PLLMUL_Pos)
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#define RCC_CFGR2_PLLMUL14 (0xCUL << RCC_CFGR2_PLLMUL_Pos)
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#define RCC_CFGR2_PLLMUL15 (0xDUL << RCC_CFGR2_PLLMUL_Pos)
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#define RCC_CFGR2_PLLMUL16 (0xEUL << RCC_CFGR2_PLLMUL_Pos)
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#define RCC_CFGR2_PREDIV_Pos 4U
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#define RCC_CFGR2_PREDIV_Msk (0x1UL << RCC_CFGR2_PREDIV_Pos)
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|
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#define RCC_APB2RST_TIM1RST_Pos 11U
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#define RCC_APB2RST_TIM1RST_Msk (0x1UL << RCC_APB2RST_TIM1RST_Pos)
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#define RCC_APB2RST_USART1RST_Pos 14U
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#define RCC_APB2RST_USART1RST_Msk (0x1UL << RCC_APB2RST_USART1RST_Pos)
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#define RCC_APB2RST_ADCRST_Pos 9U
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#define RCC_APB2RST_ADCRST_Msk (0x1UL << RCC_APB2RST_ADCRST_Pos)
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|
|
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#define RCC_APB1RST_UART1RST_Pos 18U
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#define RCC_APB1RST_UART1RST_Msk (0x1UL << RCC_APB1RST_UART1RST_Pos)
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#define RCC_APB1RST_LPUART1RST_Pos 19U
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|
#define RCC_APB1RST_LPUART1RST_Msk (0x1UL << RCC_APB1RST_LPUART1RST_Pos)
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#define RCC_APB1RST_I2C1RST_Pos 21U
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|
#define RCC_APB1RST_I2C1RST_Msk (0x1UL << RCC_APB1RST_I2C1RST_Pos)
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#define RCC_APB1RST_TIM3RST_Pos 1U
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|
#define RCC_APB1RST_TIM3RST_Msk (0x1UL << RCC_APB1RST_TIM3RST_Pos)
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|
|
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/* USART registers bit definitions */
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|
#define USART_CR1_UE_Pos 0U
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|
#define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos)
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|
#define USART_CR1_RE_Pos 2U
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|
#define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos)
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|
#define USART_CR1_TE_Pos 3U
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|
#define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos)
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|
#define USART_CR1_RXNEIE_Pos 5U
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|
#define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos)
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|
#define USART_CR1_TCIE_Pos 6U
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|
#define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos)
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|
#define USART_CR1_TXNEIE_Pos 7U
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|
#define USART_CR1_TXNEIE_Msk (0x1UL << USART_CR1_TXNEIE_Pos)
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|
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#define USART_CR1_M_Pos 12U
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|
#define USART_CR1_M_Msk (0x1UL << USART_CR1_M_Pos)
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|
#define USART_CR1_M0_Pos 12U
|
|
#define USART_CR1_M0_Msk (0x1UL << USART_CR1_M0_Pos)
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|
#define USART_CR1_M1_Pos 28U
|
|
#define USART_CR1_M1_Msk (0x1UL << USART_CR1_M1_Pos)
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|
#define USART_CR1_OVER8_Pos 15U
|
|
#define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos)
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|
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#define USART_CR3_DMAR_Pos 6U
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|
#define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos)
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#define USART_CR3_DMAT_Pos 7U
|
|
#define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos)
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|
|
#define USART_SR_RXNE_Pos 5U
|
|
#define USART_SR_RXNE_Msk (0x1UL << USART_SR_RXNE_Pos)
|
|
#define USART_SR_TC_Pos 6U
|
|
#define USART_SR_TC_Msk (0x1UL << USART_SR_TC_Pos)
|
|
#define USART_SR_TXE_Pos 7U
|
|
#define USART_SR_TXE_Msk (0x1UL << USART_SR_TXE_Pos)
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|
|
|
/* I2C registers bit definitions */
|
|
#define I2C_CR1_PE_Pos 0U
|
|
#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos)
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|
|
|
#define I2C_ISR_TXIS_Pos 1U
|
|
#define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos)
|
|
#define I2C_ISR_RXNE_Pos 2U
|
|
#define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos)
|
|
#define I2C_ISR_STOPF_Pos 5U
|
|
#define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos)
|
|
#define I2C_ISR_NACKF_Pos 4U
|
|
#define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos)
|
|
|
|
/* ADC registers bit definitions */
|
|
#define ADC_CR_ADEN_Pos 0U
|
|
#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos)
|
|
#define ADC_CR_ADDIS_Pos 1U
|
|
#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos)
|
|
#define ADC_CR_ADSTART_Pos 2U
|
|
#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos)
|
|
|
|
#define ADC_CFGR1_RES_Pos 3U
|
|
#define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos)
|
|
#define ADC_CFGR1_RES_1 (0x2UL << ADC_CFGR1_RES_Pos)
|
|
#define ADC_CFGR1_DMAEN_Pos 8U
|
|
#define ADC_CFGR1_DMAEN_Msk (0x1UL << ADC_CFGR1_DMAEN_Pos)
|
|
#define ADC_CFGR1_DMACFG_Pos 9U
|
|
#define ADC_CFGR1_DMACFG_Msk (0x1UL << ADC_CFGR1_DMACFG_Pos)
|
|
|
|
#define ADC_ISR_ADRDY_Pos 0U
|
|
#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos)
|
|
#define ADC_ISR_EOC_Pos 2U
|
|
#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos)
|
|
|
|
/* COMP (PGA) registers bit definitions */
|
|
#define COMP_CR_EN_Pos 0U
|
|
#define COMP_CR_EN_Msk (0x1UL << COMP_CR_EN_Pos)
|
|
#define COMP_CR_PGA_MODE_Pos 4U
|
|
#define COMP_CR_PGA_MODE_Msk (0x1UL << COMP_CR_PGA_MODE_Pos)
|
|
#define COMP_CR_PGA_GAIN_Pos 5U
|
|
#define COMP_CR_PGA_GAIN_Msk (0x7UL << COMP_CR_PGA_GAIN_Pos)
|
|
#define COMP_CSR_OUT_Pos 0U
|
|
#define COMP_CSR_OUT_Msk (0x1UL << COMP_CSR_OUT_Pos)
|
|
|
|
/* TIM registers bit definitions */
|
|
#define TIM_CR1_CEN_Pos 0U
|
|
#define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos)
|
|
#define TIM_CR1_CEN TIM_CR1_CEN_Msk
|
|
#define TIM_CR1_OPM_Pos 3U
|
|
#define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos)
|
|
#define TIM_CR1_ARPE_Pos 7U
|
|
#define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos)
|
|
|
|
#define TIM_DIER_UIE_Pos 0U
|
|
#define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos)
|
|
#define TIM_DIER_CC1IE_Pos 1U
|
|
#define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos)
|
|
#define TIM_DIER_CC2IE_Pos 2U
|
|
#define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos)
|
|
#define TIM_DIER_CC3IE_Pos 3U
|
|
#define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos)
|
|
#define TIM_DIER_CC4IE_Pos 4U
|
|
#define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos)
|
|
|
|
#define TIM_SR_UIF_Pos 0U
|
|
#define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos)
|
|
#define TIM_SR_CC1IF_Pos 1U
|
|
#define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos)
|
|
#define TIM_SR_CC2IF_Pos 2U
|
|
#define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos)
|
|
#define TIM_SR_CC3IF_Pos 3U
|
|
#define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos)
|
|
#define TIM_SR_CC4IF_Pos 4U
|
|
#define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos)
|
|
|
|
#define TIM_EGR_UG_Pos 0U
|
|
#define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos)
|
|
|
|
#define TIM_CCER_CC1E_Pos 0U
|
|
#define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos)
|
|
#define TIM_CCER_CC1NE_Pos 2U
|
|
#define TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos)
|
|
#define TIM_CCER_CC2E_Pos 4U
|
|
#define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos)
|
|
#define TIM_CCER_CC2NE_Pos 6U
|
|
#define TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos)
|
|
#define TIM_CCER_CC3E_Pos 8U
|
|
#define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos)
|
|
#define TIM_CCER_CC3NE_Pos 10U
|
|
#define TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos)
|
|
#define TIM_CCER_CC4E_Pos 12U
|
|
#define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos)
|
|
|
|
#define TIM_BDTR_BKE_Pos 12U
|
|
#define TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos)
|
|
#define TIM_BDTR_BKP_Pos 13U
|
|
#define TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos)
|
|
#define TIM_BDTR_AOE_Pos 14U
|
|
#define TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos)
|
|
#define TIM_BDTR_MOE_Pos 15U
|
|
#define TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos)
|
|
#define TIM_BDTR_DTG_Pos 0U
|
|
#define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos)
|
|
|
|
/* Interrupt numbers */
|
|
enum IRQn {
|
|
WWDG_IRQn = 0,
|
|
PVD_IRQn = 1,
|
|
RTC_IRQn = 2,
|
|
FLASH_IRQn = 3,
|
|
RCC_IRQn = 4,
|
|
EXTI0_1_IRQn = 5,
|
|
EXTI2_3_IRQn = 6,
|
|
EXTI4_15_IRQn = 7,
|
|
DMA1_Ch1_IRQn = 9,
|
|
DMA1_Ch2_3_IRQn = 10,
|
|
DMA1_Ch4_5_IRQn = 11,
|
|
ADC1_IRQn = 12,
|
|
TIM1_BRK_IRQn = 13,
|
|
TIM1_UP_IRQn = 14,
|
|
TIM1_TRG_LVL_IRQn = 15,
|
|
TIM1_CC_IRQn = 16,
|
|
TIM3_IRQn = 17,
|
|
TIM14_IRQn = 19,
|
|
TIM16_IRQn = 21,
|
|
TIM17_IRQn = 22,
|
|
I2C1_IRQn = 23,
|
|
SPI1_IRQn = 24,
|
|
USART1_IRQn = 25,
|
|
UART1_IRQn = 28,
|
|
LPUART1_IRQn = 29,
|
|
};
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif
|