#ifndef __CORE_CM0PLUS_H__
#define __CORE_CM0PLUS_H__

#include <stdint.h>
#include "cmsis_version.h"
#include "cmsis_compiler.h"
#include "cmsis_gcc.h"

#ifdef __cplusplus
extern "C" {
#endif

#define __CM0PLUS_REV          0x0000U
#define __MPU_PRESENT          0U
#define __VTOR_PRESENT         1U
#define __NVIC_PRIO_BITS       2U
#define __Vendor_SysTickConfig 0U

typedef struct {
    __IOM uint32_t ISER[1U];
    uint32_t RESERVED0[31U];
    __IOM uint32_t ICER[1U];
    uint32_t RESERVED1[31U];
    __IOM uint32_t ISPR[1U];
    uint32_t RESERVED2[31U];
    __IOM uint32_t ICPR[1U];
    uint32_t RESERVED3[31U];
    uint32_t RESERVED4[64U];
    __IOM uint32_t IPR[8U];
} NVIC_Type;

typedef struct {
    __IM  uint32_t CPUID;
    __IOM uint32_t ICSR;
    uint32_t RESERVED0;
    __IOM uint32_t AIRCR;
    __IOM uint32_t SCR;
    __IOM uint32_t CCR;
    uint32_t RESERVED1;
    __IOM uint32_t SHP[2U];
    __IOM uint32_t SHCSR;
} SCB_Type;

typedef struct {
    __IOM uint32_t CTRL;
    __IOM uint32_t LOAD;
    __IOM uint32_t VAL;
    __IM  uint32_t CALIB;
} SysTick_Type;

#define SCB_ACTLR_SPLISCIE_Pos       0U
#define SCB_ACTLR_SPLISCIE_Msk       (1UL << SCB_ACTLR_SPLISCIE_Pos)

#define SCB_ACTLR_DISOOFP_Pos        1U
#define SCB_ACTLR_DISOOFP_Msk        (1UL << SCB_ACTLR_DISOOFP_Pos)

#define SCB_ACTLR_DISFPCA_Pos        2U
#define SCB_ACTLR_DISFPCA_Msk        (1UL << SCB_ACTLR_DISFPCA_Pos)

#define SCB_CPUID_REVISION_Pos       20U
#define SCB_CPUID_REVISION_Msk       (0xFU << SCB_CPUID_REVISION_Pos)
#define SCB_CPUID_PARTNO_Pos          4U
#define SCB_CPUID_PARTNO_Msk          (0xFFFU << SCB_CPUID_PARTNO_Pos)
#define SCB_CPUID_CONSTANT_Pos        0U
#define SCB_CPUID_CONSTANT_Msk        (0xFU << SCB_CPUID_CONSTANT_Pos)

#define SCB_ICSR_NMIPENDSET_Pos      31U
#define SCB_ICSR_NMIPENDSET_Msk      (1UL << SCB_ICSR_NMIPENDSET_Pos)
#define SCB_ICSR_PENDSVSET_Pos       28U
#define SCB_ICSR_PENDSVSET_Msk       (1UL << SCB_ICSR_PENDSVSET_Pos)
#define SCB_ICSR_PENDSVCLR_Pos       27U
#define SCB_ICSR_PENDSVCLR_Msk       (1UL << SCB_ICSR_PENDSVCLR_Pos)
#define SCB_ICSR_PENDSTSET_Pos       26U
#define SCB_ICSR_PENDSTSET_Msk       (1UL << SCB_ICSR_PENDSTSET_Pos)
#define SCB_ICSR_PENDSTCLR_Pos       25U
#define SCB_ICSR_PENDSTCLR_Msk       (1UL << SCB_ICSR_PENDSTCLR_Pos)
#define SCB_ICSR_ISRPREEMPT_Pos      23U
#define SCB_ICSR_ISRPREEMPT_Msk      (1UL << SCB_ICSR_ISRPREEMPT_Pos)
#define SCB_ICSR_ISRPENDING_Pos      22U
#define SCB_ICSR_ISRPENDING_Msk      (1UL << SCB_ICSR_ISRPENDING_Pos)
#define SCB_ICSR_VECTPENDING_Pos     12U
#define SCB_ICSR_VECTPENDING_Msk     (0x3FFUL << SCB_ICSR_VECTPENDING_Pos)
#define SCB_ICSR_VECTACTIVE_Pos       0U
#define SCB_ICSR_VECTACTIVE_Msk       (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)

#define SCB_AIRCR_VECTKEY_Pos        16U
#define SCB_AIRCR_VECTKEY_Msk        (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
#define SCB_AIRCR_SYSRESETREQ_Pos     2U
#define SCB_AIRCR_SYSRESETREQ_Msk    (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
#define SCB_AIRCR_VECTCLRACTIVE_Msk  (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
#define SCB_AIRCR_ENDIANESS_Pos       0U
#define SCB_AIRCR_ENDIANESS_Msk      (1UL << SCB_AIRCR_ENDIANESS_Pos)

#define SCB_SCR_SEVONPEND_Pos         4U
#define SCB_SCR_SEVONPEND_Msk        (1UL << SCB_SCR_SEVONPEND_Pos)
#define SCB_SCR_SLEEPDEEP_Pos         2U
#define SCB_SCR_SLEEPDEEP_Msk        (1UL << SCB_SCR_SLEEPDEEP_Pos)
#define SCB_SCR_SLEEPONEXIT_Pos       1U
#define SCB_SCR_SLEEPONEXIT_Msk      (1UL << SCB_SCR_SLEEPONEXIT_Pos)

#define SCB_CCR_STKALIGN_Pos          9U
#define SCB_CCR_STKALIGN_Msk         (1UL << SCB_CCR_STKALIGN_Pos)
#define SCB_CCR_UNALIGN_TRP_Pos       3U
#define SCB_CCR_UNALIGN_TRP_Msk      (1UL << SCB_CCR_UNALIGN_TRP_Pos)

#define SCB_SHCSR_SVCALLPENDED_Pos   15U
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

#define SysTick_CTRL_COUNTFLAG_Pos   16U
#define SysTick_CTRL_COUNTFLAG_Msk   (1UL << SysTick_CTRL_COUNTFLAG_Pos)
#define SysTick_CTRL_CLKSOURCE_Pos    2U
#define SysTick_CTRL_CLKSOURCE_Msk   (1UL << SysTick_CTRL_CLKSOURCE_Pos)
#define SysTick_CTRL_TICKINT_Pos      1U
#define SysTick_CTRL_TICKINT_Msk     (1UL << SysTick_CTRL_TICKINT_Pos)
#define SysTick_CTRL_ENABLE_Pos       0U
#define SysTick_CTRL_ENABLE_Msk      (1UL << SysTick_CTRL_ENABLE_Pos)

#define SysTick_LOAD_RELOAD_Pos       0U
#define SysTick_LOAD_RELOAD_Msk      (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)

#define SysTick_VAL_CURRENT_Pos       0U
#define SysTick_VAL_CURRENT_Msk      (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)

#define SysTick_CALIB_TENMS_Pos       0U
#define SysTick_CALIB_TENMS_Msk      (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos)
#define SysTick_CALIB_SKEW_Pos       30U
#define SysTick_CALIB_SKEW_Msk       (1UL << SysTick_CALIB_SKEW_Pos)
#define SysTick_CALIB_NOREF_Pos      31U
#define SysTick_CALIB_NOREF_Msk      (1UL << SysTick_CALIB_NOREF_Pos)

#define SHP_START_ADDR               0xE000ED18U
#define VTOR_ADDR                    0xE000ED08U

#define NVIC_BASE                    0xE000E100U
#define SCB_BASE                     0xE000ED00U
#define SysTick_BASE                 0xE000E010U

#define NVIC                         ((NVIC_Type *)NVIC_BASE)
#define SCB                          ((SCB_Type *)SCB_BASE)
#define SysTick                      ((SysTick_Type *)SysTick_BASE)

#define NonMaskableInt_IRQn    (-14)
#define HardFault_IRQn         (-13)
#define SVCall_IRQn            (-5)
#define PendSV_IRQn            (-2)
#define SysTick_IRQn           (-1)

typedef int32_t IRQn_Type;

__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
    if ((int32_t)(IRQn) >= 0)
    {
        NVIC->IPR[(uint32_t)IRQn] = (uint32_t)(priority << (8U - __NVIC_PRIO_BITS));
    }
    else
    {
        SCB->SHP[(uint32_t)((int32_t)(IRQn) & 0xFUL) - 4UL] = (uint32_t)(priority << (8U - __NVIC_PRIO_BITS));
    }
}

__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
    if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
    {
        return 1UL;
    }

    SysTick->LOAD  = (uint32_t)(ticks - 1UL);
    NVIC_SetPriority(SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL);
    SysTick->VAL   = 0UL;
    SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
                     SysTick_CTRL_TICKINT_Msk   |
                     SysTick_CTRL_ENABLE_Msk;
    return 0UL;
}

__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
{
    if ((int32_t)(IRQn) >= 0)
    {
        return ((uint32_t)(NVIC->IPR[(uint32_t)IRQn] >> (8U - __NVIC_PRIO_BITS)));
    }
    else
    {
        return ((uint32_t)(SCB->SHP[(uint32_t)((int32_t)(IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS)));
    }
}

__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
{
    NVIC->ISER[0U] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn) & 0x1FUL);
}

__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
{
    NVIC->ICER[0U] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn) & 0x1FUL);
}

__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
    return ((uint32_t)((NVIC->ISPR[0U] >> ((uint32_t)(int32_t)IRQn)) & 1UL));
}

__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
    NVIC->ISPR[0U] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn) & 0x1FUL);
}

__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
    NVIC->ICPR[0U] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn) & 0x1FUL);
}

__STATIC_INLINE void NVIC_SystemReset(void)
{
    __DSB();
    SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
                            (SCB->AIRCR & SCB_AIRCR_ENDIANESS_Msk) |
                            SCB_AIRCR_SYSRESETREQ_Msk);
    __DSB();
    for (;;) { __NOP(); }
}

__STATIC_INLINE uint32_t SCB_GetVTOR(void)
{
    return (*(volatile uint32_t *)VTOR_ADDR);
}

__STATIC_INLINE void SCB_SetVTOR(uint32_t offset)
{
    *(volatile uint32_t *)VTOR_ADDR = offset;
}

#ifdef __cplusplus
}
#endif

#endif