2026-05-11 19:55:43 +08:00
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#include "adc_driver.h"
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#include "py32md530.h"
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#include "config.h"
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ret_code_t adc_init(void)
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{
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RCC->APB2ENR |= RCC_APB2ENR_ADCEN;
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ADC1->CR &= ~ADC_CR_ADEN_Msk;
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ADC1->CFGR1 = ADC_CFGR1_RES_1;
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2026-05-12 12:44:14 +08:00
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ADC1->CHSMPR2 = (0x7 << 3);
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2026-05-11 19:55:43 +08:00
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ADC1->SMPR1 = 0x07;
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ADC1->ISR &= ~ADC_ISR_ADRDY_Msk;
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ADC1->CR |= ADC_CR_ADEN_Msk;
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while (!(ADC1->ISR & ADC_ISR_ADRDY_Msk));
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return RET_OK;
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}
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ret_code_t adc_deinit(void)
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{
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ADC1->CR |= ADC_CR_ADDIS_Msk;
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while (ADC1->CR & ADC_CR_ADEN_Msk);
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RCC->APB2ENR &= ~RCC_APB2ENR_ADCEN;
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return RET_OK;
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}
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uint16_t adc_read_channel(adc_channel_t ch)
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{
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ADC1->CHDR1 = (uint32_t)ch;
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ADC1->ISR &= ~ADC_ISR_EOC_Msk;
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ADC1->CR |= ADC_CR_ADSTART_Msk;
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while (!(ADC1->ISR & ADC_ISR_EOC_Msk));
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return (uint16_t)(ADC1->CHDR1 & 0x0FFF);
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}
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ret_code_t adc_start_dma(uint16_t *buffer, uint32_t len)
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{
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ADC1->CFGR1 |= ADC_CFGR1_DMAEN_Msk
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| ADC_CFGR1_DMACFG_Msk;
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ADC1->CR |= ADC_CR_ADSTART_Msk;
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return RET_OK;
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}
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